The TapiComm sample uses both the Telephony API and the Win32 Communications API to demonstrate one way to implement a very simple TTY application. While the user interface and TTY emulation are very rudimentary, the TAPI and comm Modules are fairly complete.
eGroupWare is a multi-user, web-based groupware suite developed on a custom set of PHP-based APIs. Currently available Modules include: email, addressbook, calendar, infolog (notes, to-do s, phone calls), content management, forum, bookmarks, wiki
Stantor is a Domotic project. It is a SCADA for the computer interface board K8055 (USB bus), K8000 (I2C bus) , X10 Modules and also Webcam. It uses Browser WEB, I-mode and Wap2/Wap1, Apache,mySQL, PHP, javascript. It run with Linux 2.4 or 2.6 and XP
USB Manager(usbmgr) 0.4.8 Shuu Yamaguchi <shuu@wondernetworkresources.com> Special Helper: Philipp Thomas When USB devices connect to or disconnect from a USB hub, the usbmgr works as the following according to configuration. a) It loads and unloads files Linux kernel Modules. b) It execute file to setup USB devices.
The Small C compiler translates a subset of the C language into
assembly language. It runs under PC/MS-DOS 2.1 and later. Small
C is compatible with the Microsoft and Small Mac assemblers.
Small C takes full advantage of the ability of these assemblers
to generate relocatable object code, to maintain libraries of
relocatable Modules, and to link separately compiled program
Modules. It supports a small memory model with one code and one
data/stack segment.
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise.
The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
You should run "Simulation.m" function that include all Modules.
VHDL 關于2DFFT設計程序
u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be
seen in the following section.
u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus
network, and it support these sub-Modules scinode1∼ scinode9 reset and clk
and global_cnt signals to synchronous the sub-Modules to simplify the overall
design.
u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation
result.
u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow
situation.
Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory Modules implementing a pixel-level pipeline
architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is
done using a tree of carry save adders to ensure the high speed processing required for many applications.
The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis
reveals that the proposed architecture, implemented using current VLSI technologies, can process a
video stream in real time.
