<li id="euoee"></li> ·詳細(xì)說明：使用凌陽單片機(jī)的多命令語音識別范例- The use insults the positive monolithic integrated circuit the multi- orders speech recognition model 文件列表: Recognise_SD ............\bsrSD.h ............\
標(biāo)簽： 凌陽單片機(jī) 命令 語音識別 范例
上傳時間： 2013-04-24
上傳用戶：moshushi0009
·詳細(xì)說明：雙音多頻（DTMF）信號發(fā)生器的使用源程序，vc 編寫，與《雙音多頻（DTMF）接收器的使用源程序》聯(lián)合用- The double sound multi- frequencies (DTMF) the signal generating device use source program, the vc compilation, (DTMF) Receiver Use Source p
標(biāo)簽： DTMF 雙音多頻 信號發(fā)生器 源程序
上傳時間： 2013-07-23
上傳用戶：tianjinfan
·詳細(xì)說明：雙音多頻的DTMF信號編碼程序，產(chǎn)生DTMF信號進(jìn)行編碼。- The double sound multi- frequencies DTMF signal coded program, produces the DTMF signal to carry on the code.
上傳時間： 2013-04-24
上傳用戶：yangzhiwei
With more and more multi-frequency clocks being used in today's chips, especially in the communications field, it is often necessary to switch the source of a clock line while the chip is running.
上傳時間： 2013-10-10
上傳用戶：1214209695
Abstract: Using a DAC and a microprocessor supervisor, the system safety can be improved in industrial controllers, programmablelogiccontrollers (PLC), and data-acquisition systems. The analog output is set to zero-scale (or pin-programmable midscale) when amicroprocessor failure, optocoupler failure, or undervoltage condition occurs. A simple application is shown on how to implement thisfunction.
上傳時間： 2013-10-17
上傳用戶：sjb555
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
標(biāo)簽： Converters Defini DAC
上傳時間： 2013-10-30
上傳用戶：stvnash
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標(biāo)簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時間： 2013-11-12
上傳用戶：pans0ul
數(shù)字與模擬電路設(shè)計(jì)技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外，幾乎所有的電路都是由半導(dǎo)體組件所構(gòu)成，雖然半導(dǎo)體組件高速、高頻化時會有EMI的困擾，不過為了充分發(fā)揮半導(dǎo)體組件應(yīng)有的性能，電路板設(shè)計(jì)與封裝技術(shù)仍具有決定性的影響。 模擬與數(shù)字技術(shù)的融合由于IC與LSI半導(dǎo)體本身的高速化，同時為了使機(jī)器達(dá)到正常動作的目的，因此技術(shù)上的跨越競爭越來越激烈。雖然構(gòu)成系統(tǒng)的電路未必有clock設(shè)計(jì)，但是毫無疑問的是系統(tǒng)的可靠度是建立在電子組件的選用、封裝技術(shù)、電路設(shè)計(jì)與成本，以及如何防止噪訊的產(chǎn)生與噪訊外漏等綜合考慮。機(jī)器小型化、高速化、多功能化使得低頻/高頻、大功率信號/小功率信號、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數(shù)字電路，經(jīng)常出現(xiàn)在同一個高封裝密度電路板，設(shè)計(jì)者身處如此的環(huán)境必需面對前所未有的設(shè)計(jì)思維挑戰(zhàn)，例如高穩(wěn)定性電路與吵雜(noisy)性電路為鄰時，如果未將噪訊入侵高穩(wěn)定性電路的對策視為設(shè)計(jì)重點(diǎn)，事后反復(fù)的設(shè)計(jì)變更往往成為無解的夢魘。模擬電路與高速數(shù)字電路混合設(shè)計(jì)也是如此，假設(shè)微小模擬信號增幅后再將full scale 5V的模擬信號，利用10bit A/D轉(zhuǎn)換器轉(zhuǎn)換成數(shù)字信號，由于分割幅寬祇有4.9mV，因此要正確讀取該電壓level并非易事，結(jié)果造成10bit以上的A/D轉(zhuǎn)換器面臨無法順利運(yùn)作的窘境。另一典型實(shí)例是使用示波器量測某數(shù)字電路基板兩點(diǎn)相隔10cm的ground電位，理論上ground電位應(yīng)該是零，然而實(shí)際上卻可觀測到4.9mV數(shù)倍甚至數(shù)十倍的脈沖噪訊(pulse noise)，如果該電位差是由模擬與數(shù)字混合電路的grand所造成的話，要測得4.9 mV的信號根本是不可能的事情，也就是說為了使模擬與數(shù)字混合電路順利動作，必需在封裝與電路設(shè)計(jì)有相對的對策，尤其是數(shù)字電路switching時，ground vance noise不會入侵analogue ground的防護(hù)對策，同時還需充分檢討各電路產(chǎn)生的電流回路(route)與電流大小，依此結(jié)果排除各種可能的干擾因素。以上介紹的實(shí)例都是設(shè)計(jì)模擬與數(shù)字混合電路時經(jīng)常遇到的瓶頸，如果是設(shè)計(jì)12bit以上A/D轉(zhuǎn)換器時，它的困難度會更加復(fù)雜。
標(biāo)簽： 數(shù)字 模擬電路 設(shè)計(jì)技巧
上傳時間： 2013-11-16
上傳用戶：731140412
This document presents design techniques and reference circuits that power Virtex™-4 FXRocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.When using multiple transceivers, it is sometimes preferred to power them from a switchingpower supply. However, switching power supplies generate noise that affects transceiver
標(biāo)簽： RocketIO Virtex XAPP 946
上傳時間： 2013-11-18
上傳用戶：huang111
For a variety of reasons, it is desirable to charge batteriesas rapidly as possible. At the same time, overchargingmust be limited to prolong battery life. Such limitation ofovercharging depends on factors such as the choice ofcharge termination technique and the use of multi-rate/multi-stage charging schemes. The majority of batterycharger ICs available today lock the user into one fixedcharging regimen, with at best a limited number ofcustomization options to suit a variety of application needsor battery types. The LTC®1325 addresses these shortcomingsby providing the user with all the functionalblocks needed to implement a simple but highly flexiblebattery charger (see Figure 1) which not only addressesthe issue of charging batteries but also those of batteryconditioning and capacity monitoring.
上傳時間： 2013-10-19
上傳用戶：royzhangsz
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
