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  • An AHB system is made of masters slaves and interconnections. A general approach to include all poss

    An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.

    標簽: interconnections approach general include

    上傳時間: 2015-12-12

    上傳用戶:lyy1234

  • In a preemptive priority based RTOS, priority inversion problem is among the major sources of deadl

    In a preemptive priority based RTOS, priority inversion problem is among the major sources of deadline violations. Priority inheritance protocol is one of the approaches to reduce priority inversion. Unfortunately, RTOS like uC/OS can’t support priority inheritance protocol since it does not allow kernel to have multiple tasks at the same priority. Although it has different ways to avoid priority inversion such as priority ceiling protocol, developers still have some difficulties in programming real time applications with it. In this paper, we redesign the uC/OS kernel to provide the ability to support round robin scheduling and implement priority inheritance semaphore on the modified kernel. As result, we port new kernel with priority inheritance semaphore to evaluation board, and evaluate the execution time of each of the kernel service as well as verify the operations of our implementation.

    標簽: priority preemptive inversion problem

    上傳時間: 2015-12-14

    上傳用戶:氣溫達上千萬的

  • As the Hardware Description Language (HDL) enhancement activities have increased over the past year,

    As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.

    標簽: Description enhancement activities the

    上傳時間: 2015-12-15

    上傳用戶:sunjet

  • As the Hardware Description Language (HDL) enhancement activities have increased over the past year,

    As the Hardware Description Language (HDL) enhancement activities have increased over the past year, so too has the complexity in determining which language(s) are the best tools for designers and organizations to continue using or to adopt. Many designers and organizations are contemplating whether they should switch from one HDL to another.

    標簽: Description enhancement activities the

    上傳時間: 2015-12-15

    上傳用戶:SimonQQ

  • FuncPlotter is a combined Java application and applet for displaying two-dimensional plots of explic

    FuncPlotter is a combined Java application and applet for displaying two-dimensional plots of explicit functions in one variable (ie, FuncPlotter plots functions of the form y = f(x), where f(x) is composed from common mathematical operators).

    標簽: two-dimensional FuncPlotter application displaying

    上傳時間: 2015-12-16

    上傳用戶:妄想演繹師

  • this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu

    this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.

    標簽: implementation include quartus source

    上傳時間: 2013-12-25

    上傳用戶:壞壞的華仔

  • DAGON Approach Object of this exercise: Given a subject graph and a set of pattern graph in canoni

    DAGON Approach Object of this exercise: Given a subject graph and a set of pattern graph in canonical representation (2-input NAND and INV), implement the second step of DAGON approach. (Both the subject graph and the pattern graphs are trees.)

    標簽: graph Approach exercise subject

    上傳時間: 2014-01-19

    上傳用戶:stampede

  • LCDScreen is a couple of Delphi component which simulate a dot-LCD multilines screen. It is fully c

    LCDScreen is a couple of Delphi component which simulate a dot-LCD multilines screen. It is fully customizable and has animation and special effects capabilities for the displayed text. TLCDScreen is the display component and TLCDAnimator the animation one. Both have build-in Property editor making easier the development at design-time.

    標簽: multilines LCDScreen component simulate

    上傳時間: 2015-12-23

    上傳用戶:invtnewer

  • New users and old of optimization in MATLAB will find useful tips and tricks in this document, as we

    New users and old of optimization in MATLAB will find useful tips and tricks in this document, as well as examples one can use as templates for their own problems. Use this tool by editing the file optimtips.m, then execute blocks of code in cell mode from the editor, or best, publish the file to HTML. Copy and paste also works of course. Some readers may find this tool valuable if only for the function pleas - a partitioned least squares solver based on lsqnonlin. This is a work in progress, as I fully expect to add new topics as I think of them or as suggestions are made. Suggestions for topics I ve missed are welcome, as are corrections of my probable numerous errors. The topics currently covered are listed below

    標簽: optimization and document MATLAB

    上傳時間: 2015-12-24

    上傳用戶:佳期如夢

  • This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block

    This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.

    標簽: block-by-block acquired example streams

    上傳時間: 2015-12-29

    上傳用戶:bjgaofei

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