Three-dimensional real-time graphics are a prevalent technology nowadays, thanks to the steady rise of processing power and specialized graphics hardware. One of the goals of computer graphics most sought after and difficult to achieve is to reproduce realistic outdoor environments featuring dense forests.
標(biāo)簽： Three-dimensional technology real-time prevalent
上傳時(shí)間： 2014-01-15
上傳用戶：壞天使kk
一個(gè)開源heml語意分析器 ekhtml: The El-Kabong HTML parser SUMMARY: El-Kabong: A speedy, yet forgiving, SAX-stylee HTML parser. PROJECT INFORMATION: Web Site: ekhtml.sourceforge.net The web site contains links to locations where one can: - file bugs - join mailing lists - download the latest release - browse documentation - get CVS information BUILDING: See the file INSTALL for information、目標(biāo)代碼生成、符號(hào)表的構(gòu)造和運(yùn)行時(shí)存儲(chǔ)空間的組織等8部分組成。
標(biāo)簽： El-Kabong forgiving SUMMARY ekhtml
上傳時(shí)間： 2014-12-08
上傳用戶：dapangxie
/* Check_SST_39VF400A Check manufacturer and device ID /* CFI_Query CFI Query Entry/Exit command sequence /* Erase_One_Sector Erase a sector of 2048 words /* Erase_One_Block Erase a block of 32K words /* Erase_Entire_Chip Erase the contents of the entire chip /* Program_One_Word Alter data in one word /* Program_One_Sector Alter data in 2048 word sector /* Program_One_Block Alter data in 32K word block
標(biāo)簽： manufacturer Check_SST CFI_Query command
上傳時(shí)間： 2013-12-15
上傳用戶：jjj0202
Implemented BFS, DFS and A* To compile this project, use the following command: g++ -o search main.cpp Then you can run it: ./search The input is loaded from a input file in.txt Here is the format of the input file: The first line of the input file shoud contain two chars indicate the source and destination city for breadth first and depth first algorithm. The second line of input file shoud be an integer m indicate the number of connections for the map. Following m lines describe the map, each line represents to one connection in this form: dist city1 city2, which means there is a connection between city1 and city2 with the distance dist. The following input are for A* The following line contains two chars indicate the source and destination city for A* algorithm. Then there is an integer h indicate the number of heuristic. The following h lines is in the form: city dist which means the straight-line distance from the city to B is dist.
標(biāo)簽： Implemented following compile command
上傳時(shí)間： 2014-01-01
上傳用戶：lhc9102
Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.
標(biāo)簽： symbols length Hard-decision Codeword
上傳時(shí)間： 2014-07-08
上傳用戶：曹云鵬
使用到的參數(shù)跟談到彈性網(wǎng)絡(luò)的那一章里頭所講的是一樣的， ke 則是終止條件。如果 step 被打勾，則程式在每一步之間會(huì)暫停 100毫秒（或其他使用者輸入的數(shù)值）。如果 Random 被打勾，則程式會(huì)以系統(tǒng)時(shí)間作為亂數(shù)產(chǎn)生器的種子數(shù)，否則，就以使用者輸入的數(shù)（ Random 右邊那一格）為種子數(shù)。 你可以利用 load 來載入推銷員問題檔與其最佳解，如此便可比較彈性網(wǎng)絡(luò)所找出來的解與最佳解差了多少。 Central, Radius, and Error 這三個(gè)參數(shù)的前兩個(gè)，只影響彈性網(wǎng)絡(luò)的起使位置和大小，對(duì)求解沒有影響。第三個(gè)參數(shù)代表城市與網(wǎng)絡(luò)點(diǎn)之間的容忍距離，也就是說，如果某城市與某網(wǎng)絡(luò)點(diǎn)之間的距離，小于容忍距離，那就把這個(gè)城市當(dāng)成是被該網(wǎng)絡(luò)點(diǎn)所拜訪。 按下小 w按鈕會(huì)將目前的結(jié)果與參數(shù)值寫到“en.out”這個(gè)檔案。使得我們可以很方便地來比較不同參數(shù)的效果。
標(biāo)簽： 參數(shù) 彈性 網(wǎng)絡(luò)
上傳時(shí)間： 2013-12-17
上傳用戶：84425894
it contains many classic Test Problems for Unconstrained Optimization such as camel6,treccani,goldstein,branin, shubert1,Ackley,dejong,dejong1,dejong2, dpower,rastrigin,Griewangk,Schwefel, rosenbrock2 and step. the package have the contour and mesh figures of these problem. it also give m files of these problems,and you can easily get your view of figures.
標(biāo)簽： Unconstrained Optimization contains Problems
上傳時(shí)間： 2015-09-17
上傳用戶：bcjtao
Robustnesstochangesinilluminationconditionsaswellas viewing perspectives is an important requirement formany computer vision applications. One of the key fac-ors in enhancing the robustness of dynamic scene analy-sis that of accurate and reliable means for shadow de-ection. Shadowdetectioniscriticalforcorrectobjectde-ection in image sequences. Many algorithms have beenproposed in the literature that deal with shadows. How-ever,acomparativeevaluationoftheexistingapproachesisstill lacking. In this paper, the full range of problems un-derlyingtheshadowdetectionareidenti?edanddiscussed.Weclassifytheproposedsolutionstothisproblemusingaaxonomyoffourmainclasses, calleddeterministicmodeland non-model based and statistical parametric and non-parametric. Novelquantitative(detectionanddiscrimina-ionaccuracy)andqualitativemetrics(sceneandobjectin-dependence,?exibilitytoshadowsituationsandrobustnesso noise) are proposed to evaluate these classes of algo-rithms on a benchmark suite of indoor and outdoor videosequences.
標(biāo)簽： Robustnesstochangesinillumination conditionsaswellas perspectives requirement
上傳時(shí)間： 2014-01-23
上傳用戶：whenfly
//Basic packet sending test at the MAC level, used for internal testing only. //This packet test has one node sending out a variety of //differently formatted packets to two assumed destination nodes.
標(biāo)簽： packet test internal sending
上傳時(shí)間： 2014-08-21
上傳用戶：CSUSheep
Verilog and VHDL狀態(tài)機(jī)設(shè)計(jì)，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
標(biāo)簽： Verilog VHDL and 狀態(tài)
上傳時(shí)間： 2013-12-19
上傳用戶：change0329
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