This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight Outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽： CoolRunner-II XAPP CPLD 380
上傳時(shí)間： 2013-10-26
上傳用戶：kiklkook
在Protel2004中進(jìn)行PCB的完備的CAM輸出。首先，我們可以輸出的gerber文件， 操作如下：1：畫好PCB后，在PCB 的文件環(huán)境中，左鍵點(diǎn)擊File\Fabrication Outputs\Gerber Files,進(jìn)入Gerber setup 界面
標(biāo)簽： Designer Altium CAM PCB
上傳時(shí)間： 2013-11-24
上傳用戶：sevenbestfei
用LPC213X系列的PWM來產(chǎn)生語音。語音數(shù)據(jù)來源于PC機(jī)轉(zhuǎn)換后得到的。最大可以是16位的。 由于是PWM所以輸出端口需要低通濾波才能夠得到比較干凈的聲音。 可以經(jīng)過修改使用LPC2132以上的ARM的D/A來產(chǎn)生。 This project Outputs audio on PWM0 using wave samples that are stored in the on-chip Flash ROM.
上傳時(shí)間： 2014-11-07
上傳用戶：zhanditian
This example program shows how to configure and use the A/D Converter of the following microcontroller: STMicroelectronics ST10F166 After configuring the A/D, the program reads the A/D result and Outputs the converted value using the serial port. To run this program... Build the project (Project Menu, Build Target) Start the debugger (Debug Menu, Start/Stop Debug Session) View the Serial Window (View Menu, Serial Window #1) View the A/D converter peripheral (Peripheral Menu, A/D Converter) Run the program (Debug Menu, Go) A debug script (debug.ini) creates buttons that set different analog values in A/D channels. As the program runs, you will see the A/D input and output change. Other buttons create signals that generate sine wave or sawtooth patterns as analog inputs. µ Vision3 users may enable the built-in Logic Analyzer to view, measure and compare these input signals graphically.
標(biāo)簽： microcontroll Converter configure following
上傳時(shí)間： 2014-12-01
上傳用戶：獨(dú)孤求源
EXAMPLE SOURCE CODE FOR IMPLIB FILTER This filter accepts input through the standard input stream, convertsit and Outputs it to the standard output am. The streams are linkedthrough pipes, such that the input stream is the output from the import librarian being invoked, and the output stream is connected to the message window of the IDE, ie.
標(biāo)簽： input standard EXAMPLE accepts
上傳時(shí)間： 2014-11-18
上傳用戶：siguazgb
EXAMPLE SOURCE CODE FOR TASM FILTER his filter accepts input through the standard input stream, converts it and Outputs it to the standard output stream. The streams are linked through pipes, such that the input stream is the output from the assembler being invoked, and the output stream is connected to the message window of the IDE, ie.
標(biāo)簽： input standard EXAMPLE accepts
上傳時(shí)間： 2014-01-13
上傳用戶：小碼農(nóng)lz
The 74ALVC16245(74ALVCH16245) is a 16-bit transceiver featuring non-inverting 3-State bus compatible Outputs in both send and receive directions.
標(biāo)簽： 16245 non-inverting transceiver featuring
上傳時(shí)間： 2013-12-21
上傳用戶：風(fēng)之驕子
Generate a great circle "trajectory" from [lat1,lon1] to [lat2, lon2]. ％ Resulting points will be seperated by approximately delta_ft feet. ％ By default, delta_ft = 100 feet. All lat/lon inputs & Outputs are in ％ degrees.
標(biāo)簽： trajectory Resulting lat Generate
上傳時(shí)間： 2014-01-01
上傳用戶：璇珠官人
// This program demonstrates how to configure the C8051F060 to write to and read // from the UART interface. The program reads a word using the UART0 interrupts // and Outputs that word to the screen, with all characters in uppercase
標(biāo)簽： demonstrates C8051F060 configure the
上傳時(shí)間： 2013-12-23
上傳用戶：hopy
vhdl編寫，8b—10b 編解碼器設(shè)計(jì) Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO Outputs 8-bit parallel unencoded output valid 1 clock later
上傳時(shí)間： 2016-05-05
上傳用戶：gundamwzc
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