The SL74HC573 is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS Outputs with pullup
resistors, they are compatible with LS/ALSTTL Outputs.
These latches appear transparent to data (i.e., the Outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The SP486 and SP487 are low–power quad differential line drivers meeting RS-485 and RS-422
standards. The SP486 features a common driver enable control the SP487 provides independent
driver enable controls for each pair of drivers. Both feature tri–state Outputs and wide
common–mode input range. Both are available in 16–pin plastic DIP and SOIC packages.
This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288).
Image resolution is not limited. It takes an RGB input (row-wise) and Outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
This program implements a PIC-based fuzzy inference engine for the Fudge fuzzy development system from Motorola.
It works by taking the output from Fudge for the 68HC11 processor, and converting it to a MPASM compatible assembler file using the convert
batch file.
This file can then be incorporated with fuzzy.asm to create a fuzzy inference engine.
Tool chain
----------
FUDGE -> Fuzzy Rules -> MC68HC11.ASM -> CONVERT.BAT -> RULES.ASM
-> MPASM FUZZY.ASM -> INTEL HEX
Fuzzy input registers
---------------------
current_ins 1..8 x 8-bit raw inputs
Fuzzy inference function
------------------------
FuzzyEngine
Fuzzy output registers
----------------------
cog_outs 1..8 x 8-bit raw Outputs
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM.
The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and Outputs an IMA ADPCM compressed WAV file.
Compression ratio is fixed for IMA-ADPCM, being 4:1.
PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Commons Attribution-Noncommercial-Share Alike 3.0 Unported). That means you may use it only for NON-COMMERCIAL purposes.
-- Hamming Decoder
-- This Hamming decoder accepts an 8-bit Hamming code (produced by the encoder above) and performs single error correction and double error detection.
-- download from: www.pld.com.cn & www.fpga.com.cn
LIBRARY ieee
USE ieee.std_logic_1164.ALL
ENTITY hamdec IS
PORT(hamin : IN BIT_VECTOR(0 TO 7) --d0 d1 d2 d3 p0 p1 p2 p4
dataout : OUT BIT_VECTOR(0 TO 3) --d0 d1 d2 d3
sec, ded, ne : OUT BIT) --diagnostic Outputs
END hamdec
ARCHITECTURE ver1 OF hamdec IS
BEGIN
RS_latch using vhdl,
When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q.
Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q Outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
In 揚erformance of multi-carrier DS CDMA Systems?we apply a multi-carrier signaling technique to a direct-sequence CDMA system, where a data sequence multiplied by a spreading sequence modulates multiple carriers, rather than a single carrier. The receiver provides a correlator for each carrier, and the Outputs of the correlators are combined with a maximal-ratio combiner. This type of signaling has the desirable properties of exhibiting a narrowband interference suppression effect, along with robustness to fading, without requiring the use of either an explicit RAKE structure or an interference suppression filter.
ADIAL Basis Function (RBF) networks were introduced
into the neural network literature by Broomhead and
Lowe [1], which are motivated by observation on the local
response in biologic neurons. Due to their better
approximation capabilities, simpler network structures and
faster learning algorithms, RBF networks have been widely applied in many science and engineering fields. RBF network is three layers feedback network, where each hidden unit implements a radial activation function and each output unit implements a weighted sum of hidden units’ Outputs.
