This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
See Appendix B for a description of the programs included on this companion disk. RESOURCE.WRI identifies other books and resources for Internet programming. WEBHELP.HLP contains an introduction to the World Wide Web. TCPMAN.HLP provides detailed instructions to help you use the Trumpet Winsock included on this disk. Use the Program Manager s File menu Run option to execute the SETUP.EXE program found on this disk. SETUP.EXE will install the programs on your hard drive and create an Internet Programming group window. Internet編程技術 [配套程序] [涉及平臺] VC [作者] void [文件大小] 1032K
標簽： description companion Appendix RESOURCE
上傳時間： 2013-12-04
上傳用戶：asasasas
* "Copyright (c) 2006 Robert B. Reese ("AUTHOR")" * All rights reserved. * (R. Reese, reese@ece.msstate.edu, Mississippi State University) * IN NO EVENT SHALL THE "AUTHOR" BE LIABLE TO ANY PARTY FOR * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHOR" * HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
上傳時間： 2015-09-24
上傳用戶：mpquest
This I develops based on the B/S structure student managementsystem management system, hoped brings a help to the novice
標簽： managementsystem management structure develops
上傳時間： 2014-01-07
上傳用戶：釣鰲牧馬
Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
標簽： representation Magnitude the magnitude
上傳時間： 2013-12-24
上傳用戶：金宜
design LP,HP,B S digital Butterworth and Chebyshev filter. All array has been specified internally,so user only need to input f1,f2,f3,f4,fs(in hz), alpha1,alpha2(in db) and iband (to specify the type of to design). This program output hk(z)=bk(z)/ak(z),k=1,2,..., ksection and the freq.
標簽： Butterworth internally Chebyshev specified
上傳時間： 2015-11-08
上傳用戶：253189838
About: hamsterdb is a database engine written in ANSI C. It supports a B+Tree index structure, uses memory mapped I/O (if available), supports cursors, and can create in-memory databases. Release focus: Major feature enhancements Changes: This release comes with many changes and new features. It can manage multiple databases in one file. A new flag (HAM_LOCK_EXCLUSIVE) places an exclusive lock on the file. hamsterdb was ported to Windows CE, and the Solution file for Visual Studio 2005 now supports builds for x64. Several minor bugs were fixed, performance was improved, and small API changes occurred. Pre-built libraries for Windows (32-bit and 64-bit) are available for download. Author: cruppstahl
標簽： C. hamsterdb structure database
上傳時間： 2013-12-11
上傳用戶：LouieWu
Floyd-Warshall算法描述 1)適用范圍： a)APSP(All Pairs Shortest Paths) b)稠密圖效果最佳 c)邊權可正可負 2)算法描述： a)初始化：dis[u,v]=w[u,v] b)For k:=1 to n For i:=1 to n For j:=1 to n If dis[i,j]>dis[i,k]+dis[k,j] Then Dis[I,j]:=dis[I,k]+dis[k,j] c)算法結束：dis即為所有點對的最短路徑矩陣 3)算法小結：此算法簡單有效，由于三重循環結構緊湊，對于稠密圖，效率要高于執行|V|次Dijkstra算法。時間復雜度O(n^3)。 考慮下列變形：如(I,j)∈E則dis[I,j]初始為1,else初始為0，這樣的Floyd算法最后的最短路徑矩陣即成為一個判斷I,j是否有通路的矩陣。更簡單的，我們可以把dis設成boolean類型，則每次可以用“dis[I,j]:=dis[I,j]or(dis[I,k]and dis[k,j])”來代替算法描述中的藍色部分，可以更直觀地得到I,j的連通情況。
標簽： Floyd-Warshall Shortest Pairs Paths
上傳時間： 2013-12-01
上傳用戶：dyctj
PCI設計指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.
標簽： interface PCI pre-implemented LogiCORE
上傳時間： 2016-04-03
上傳用戶：清風冷雨
The Cyclone® III PCI development board provides a hardware platform for developing and prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a high-density of the memory to facilitate the design and development of FPGA designs which need huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
標簽： development developing prototypi provides
上傳時間： 2017-01-29
上傳用戶：jjj0202
