ARM核心是主控SOC中的重要部分，系統的日常應用都由ARM核心來完成，因此ARM核心的效能很大程度上跟用戶體驗有關。ARM公司一般用DMIPS/MHz來標稱ARM核心的性能。DMIPS是Dhrystone Million Instructions executed PER Second的縮寫，反映核心的整數計算能力。但Dhrystone算法代碼本身比較叫，可以完全放到Cache中執行，因此反映的只是核心能力，并不能反映緩存、內存I/O性能。
本軟件是關于MAX338, MAX339的英文數據手冊：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復用器
The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions.
These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, PER method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits PER second will remain the same.
This application note covers the design considerations of a system using the PERformance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits PER pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
PERformance monitor blocks are added to capture PERformance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
function y_cum = cum2x (x,y, maxlag, nsamp, overlap, flag)
％CUM2X Cross-covariance
％ y_cum = cum2x (x,y,maxlag, samp_seg, overlap, flag)
％ x,y - data vectors/matrices with identical dimensions
％ if x,y are matrices, rather than vectors, columns are
％ assumed to correspond to independent realizations,
％ overlap is set to 0, and samp_seg to the row dimension.
％ maxlag - maximum lag to be computed [default = 0]
％ samp_seg - samples PER segment [default = data_length]
％ overlap - PERcentage overlap of segments [default = 0]
％ overlap is clipped to the allowed range of [0,99].
The Staged Event-Driven Architecture (SEDA) is a new design for building scalable Internet services. SEDA has three major goals:
To support massive concurrency, on the order of tens of thousands of clients PER node
To exhibit robust PERformance under wide variations in load and,
To simplify the design of complex Internet services.
SEDA decomposes a complex, event-driven application into a set of stages connected by queues. This design avoids the high overhead associated with thread-based concurrency models, and decouples event and thread scheduling from application logic. SEDA enables services to be well-conditioned to load, preventing resources from being overcommitted when demand exceeds service capacity. Decomposing services into a set of stages also enables modularity and code reuse, as well as the development of debugging tools for complex event-driven applications.
Delphi and C++ Builder component for direct access to IO ports on Windows 95, Windows 98 and Windows NT/2000. Provides proPERties for reading and writing bytes, words and doublewords from/to IO ports. New fast block data transfer methods enable to read and write megabytes of data PER second.
Input
The input contains blocks of 2 lines. The first line contains the number of sticks parts after cutting, there are at most 64 sticks. The second line contains the lengths of those parts separated by the space. The last line of the file contains zero.
Output
The output should contains the smallest possible length of original sticks, one PER line.
Sample Input
9
5 2 1 5 2 1 5 2 1
4
1 2 3 4
0
Sample Output
6
5
This document provides guidelines for integrating a discrete high speed USB host controller onto a fourlayer
desktop motherboard. The material covered can be broken into three main categories: Board design
guidelines, EMI/ESD guidelines and front panel USB guidelines. Section 1.1 Background provides an
explanation of the routing exPERiments and testing PERformed to validate the feasibility of 480 Megabits PER
second on an actual motherboard. Section 7 contains a design checklist that lists each design
recommendation described in this document. High speed USB oPERation is described in the USB 2.0
Specification (http://www.usb.org/develoPERs/docs.html).
