WP369可擴展式處理平臺-各種嵌入式系統的理想解決方案 ：Delivering unrivaled levels of system PERFORMANCE,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
This application note covers the design considerations of a system using the PERFORMANCE
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
PERFORMANCE monitor blocks are added to capture PERFORMANCE data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
XAPP520將符合2.5V和3.3V I/O標準的7系列FPGA高性能I/O Bank進行連接
The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high PERFORMANCE (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-PERFORMANCE computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
Abstract: High-PERFORMANCE base-station (BTS) receivers must meet half-IF spurious requirements, whichcan be achieved by using the proper RF mixer. To help engineers, this application note illustrates the
為提升虛擬儀器傳輸速率與實時性能，擴展監測范圍，在VC的軟件平臺上設計了一種全功能虛擬示波器。與傳統虛擬示波器相比，該系統采用嵌入式系統完成信號采集，采用工業以太網為傳輸介質，通過線性插值算法和多線程編程思想，實現波形顯示、參數計算、頻譜分析以及波形存儲及回放功能。實驗結果表明，該虛擬示波器可以實現20 kHz采樣頻率下的波形精確顯示，達到預期的各項指標。
Abstract:
o enhance the transfer rate and real-time of virtual instrument PERFORMANCE， expand scope of monitoring， this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope， this system adopts the embedded system to complete the data acquisition， industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas， namely to achieve waveform display， parameter calculation， spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency， and achieve the desired targets.
Abstract: This reference design provides design ideas for a cost-effective, low-power liquid-level measurement dataacquisition system (DAS) using a compensated silicon pressure sensor and a high-precision delta-sigma ADC. Thisdocument discusses how to select the compensated silicon pressure sensor, suggest system algorithms, and providenoise analyses. It also describes calibration ideas to improve system PERFORMANCE while also reducing complexity andcost.
多遠程二極管溫度傳感器-Design Considerations for pc thermal management
Multiple RDTS (remote diode temperature sensing) provides the most accurate method of sensing an IC’s junction temperature. It overcomes thermal gradient and placement issues encountered when trying to place external sensors. PCB component count decreases when using a device that provides multiple inputs.Better temperature sensing improves product PERFORMANCE and reliability. Disk drive data integrity suffers at elevated temperatures. IBM published an article stating that a 5°C rise in operating temperature causes a 15% increase in the drive’s failure rate. The overall PERFORMANCE of a system can be improved by providing a more accurate temperature measurement of the most critical devices allowing them to run just a few degrees hotter.The LM83 directly senses its own temperature and the temperature of three external PN junctions. One is dedicated to the CPU of choice, the other two go to other parts of your system that need thermal monitoring such as the disk drive or graphics chip. The SMBus-compatible LM83 supports SMBus timeout and logic levels. The LM83 has two interrupt outputs; one for user-programmable limits and WATCHDOG capability (INT), the other is a Critical Temperature Alarm output (T_CRIT_A) for system power supply shutdown.
Abstract: Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signalprocessing, medical imaging, and high-PERFORMANCE computing. This application note outlines the issues related to powering FPGAs.It also discusses Maxim's solutions for powering Xilinx® FPGAs.
This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) PERFORMANCE testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run PERFORMANCE tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
