this a pack include source code for quartus 2.
It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the PROCESSOR and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
This document is an operation guide for the MPC8XXFADS board. It contains operational, functional
and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/
w and h/w development around the MPC8XX family PROCESSORs. Using its on-board resources and its
associated debugger, a developer is able to download his code, run it, set breakpoints, display
memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated
to a desired system with the MPC8XX PROCESSOR.
=== === === === === === === === === === ====
IBM PC KEYBOARD INFORMATION FOR SOFTWARE DEVELOPERS
================================================================
Sources:
PORTS.A of Ralf Brown s interrupt list collection
repairfaq.org keyboard FAQ(doesn t appear to exsist)
Linux source code
Test hardware:
New Samsung KB3T001SAXAA 104-key keyboard
Old Maxi 2186035-00-21 101-key keyboard
NO WARRANTY. NO GUARANTEE. I have tried to make this information
accurate. I don t know if I succeeded. Corrections or additional
information would be welcome.
This is a plain-text document. If you use a word-PROCESSOR to view
it, use a fixed-pitch font (like Courier) so columnar data and
ASCII art lines up properly.
This the source release kit for the following system configuration(s):
- AMD Alchemy(TM) DBAu1200(TM) and AMD Alchemy(TM) Pb1200(TM)
development boards (AMD Alchemy(TM) Au1200(TM) PROCESSOR)
- Windows CE 5.0
- RMI Au1200 Core BSP v1.51
- RMI Au1200 Media BSP v1.51
SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief
description of each sub-section. The design consists of:
· PowerPC PROCESSOR
· PLB-OPB bridge
· BlockRAM Memory Controller
· SDRAM Controller
· Two GPIO ports
· A UART Port
· External SDRAM
The PCI Local bus concept was developed to break
the PC data I/O bottleneck and clearly opens the door
to increasing system speed and expansion capabilities.
The PCI Local bus moves high speed peripherals
from the I/O bus and places them closer to the system’s
PROCESSOR bus, providing faster data transfers
between the PROCESSOR and peripherals. The PCI Local
bus also addresses the industry’s need for a bus standard
which is not directly dependent on the speed,
size and type of system PROCESSOR. It represents the
first microPROCESSOR independent bus offering performance
more than adequate for the most demanding
applications such as full-motion video.
The PCI Local bus concept was developed to break
the PC data I/O bottleneck and clearly opens the door
to increasing system speed and expansion capabilities.
The PCI Local bus moves high speed peripherals
from the I/O bus and places them closer to the system’s
PROCESSOR bus, providing faster data transfers
between the PROCESSOR and peripherals. The PCI Local
bus also addresses the industry’s need for a bus standard
which is not directly dependent on the speed,
size and type of system PROCESSOR. It represents the
first microPROCESSOR independent bus offering performance
more than adequate for the most demanding
applications such as full-motion video.
Hardware reference
