This library implements the KLT Tracking algorithm [2004] for Feature Tracking in Video useful in computer vision tasks like object recognition, image indexing, tracking and structure from motion. This implementation uses PROGRAMMABLE Graphics Hardware to achieve considerable speedup in the running time of the GPU-based implementation.
In this work an implementation of a geometric nonlinear controller for chaos synchronization in a Field PROGRAMMABLE Gate Array (FPGA) is presented. The Lorenz chaotic system is used to show the implementation of chaos synchronization via nonlinear controller implemented in a Xilinx FPGA Virtex-II 2v2000ft896-4. The main idea is to design a nonlinear geometric controller which synchronizes a slave Lorenz system to a master system and then implement them into the FPGA.
In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field PROGRAMMABLE Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx
Alliance tools and Synplicity Synplify.
A spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (Field PROGRAMMABLE Gate Array) implementation in present paper.
Commercially available active noise control headphones rely on fixed analog controllers to drive "anti-noise" loudspeakers. Our design uses an adaptive controller to optimally cancel unwanted acoustic noise. This headphone would be particularly useful for workers who operate or work near heavy machinery and engines because the noise is selectively eliminated. Desired sounds, such as speech and warning signals, are left to be heard clearly. The adaptive control algorithm is implemented on a Texas Instruments (TI™ )
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TMS320C30GEL digital signal processor (DSP), which drives a Sony CD550 headphone/microphone system. Our experiments indicate that adaptive noise control results in a dramatic improvement in performance over fixed noise control. This improvement is due to the availability of high-performance PROGRAMMABLE DSPs and the self-optimizing and tracking
capabilities of the adaptive controller in response to the surrounding noise.
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-PROGRAMMABLE, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is PROGRAMMABLE with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core.
TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms.
The TAS3204 contains a custom-designed, fully-PROGRAMMABLE 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations.
Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference.
The TAS3204 is composed of eight functional blocks:
Clocking System
Digital Audio Interface
Analog Audio Interface
Power supply
Clocks, digital PLL
I2C control interface
8051 MCUcontroller
Audio DSP – digital audio processing
特性
Digital Audio Processor
Fully PROGRAMMABLE With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment
135-MHz Operation
48-Bit Data Path With 76-Bit Accumulator
Hardware Single-Cycle Multiplier (28 × 48)
AEC-Q100 qualified
? 12 V and 24 V battery systems compliance
? 3.3 V and 5 V logic compatible I/O
? 8-channel configurable MOSFET pre-driver
– High-side (N-channel and P-channel MOS)
– Low-side (N-channel MOS)
– H-bridge (up to 2 H-bridge)
– Peak & Hold (2 loads)
? Operating battery supply voltage 3.8 V to 36 V
? Operating VDD supply voltage 4.5 V to 5.5 V
? All device pins, except the ground pins, withstand at least 40 V
? PROGRAMMABLE gate charge/discharge currents for improving EMI behavior
New applications such as video conferencing, video on demand, multi-
media transcoders, Voice-over-IP (VoIP), intrusion detection, distributed
collaboration, and intranet security require advanced functionality from
networks beyond simple forwarding congestion control techniques.
