Xilinx UltraScale™ 架構針對要求最嚴苛的應用，提供了前所未有的ASIC級的系統級集成和容量。 UltraScale架構是業界首次在All PROGRAMMABLE架構中應用最先進的ASIC架構優化。該架構能從20nm平面FET結構擴展至16nm鰭式FET晶體管技術甚至更高的技術，同 時還能從單芯片擴展到3D IC。借助Xilinx Vivado®設計套件的分析型協同優化，UltraScale架構可以提供海量數據的路由功能，同時還能智能地解決先進工藝節點上的頭號系統性能瓶頸。 這種協同設計可以在不降低性能的前提下達到實現超過90%的利用率。 UltraScale架構的突破包括： • 幾乎可以在晶片的任何位置戰略性地布置類似于ASIC的系統時鐘，從而將時鐘歪斜降低達50% • 系統架構中有大量并行總線，無需再使用會造成時延的流水線，從而可提高系統速度和容量 • 甚至在要求資源利用率達到90%及以上的系統中，也能消除潛在的時序收斂問題和互連瓶頸 • 可憑借3D IC集成能力構建更大型器件，并在工藝技術方面領先當前行業標準整整一代 • 能在更低的系統功耗預算范圍內顯著提高系統性能，包括多Gb串行收發器、I/O以及存儲器帶寬 • 顯著增強DSP與包處理性能 賽靈思UltraScale架構為超大容量解決方案設計人員開啟了一個全新的領域。
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-17
上傳用戶：皇族傳媒
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All PROGRAMMABLE architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/PROGRAMMABLE electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and PROGRAMMABLE electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-05
上傳用戶：維子哥哥
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-PROGRAMMABLE gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽： PicoBlaze Create Master Xilinx
上傳時間： 2013-11-05
上傳用戶：a6697238
Designing withPROGRAMMABLE Logicin an Analog WorldPROGRAMMABLE logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex PROGRAMMABLE logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標簽： Solutions Analog Xilinx FPGAs
上傳時間： 2013-11-01
上傳用戶：a67818601
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully PROGRAMMABLE alternative to ASSPs and ASICs.
上傳時間： 2014-12-28
上傳用戶：zhang97080564
WP369可擴展式處理平臺-各種嵌入式系統的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm PROGRAMMABLE logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上傳時間： 2013-10-22
上傳用戶：685
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s PROGRAMMABLE imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm PROGRAMMABLE logic—in a single device. The processor boots first, prior to configuration of the PROGRAMMABLE logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上傳時間： 2013-11-01
上傳用戶：dingdingcandy
Field PROGRAMMABLE Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上傳時間： 2013-10-29
上傳用戶：lixqiang
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a PROGRAMMABLE interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2014-11-29
上傳用戶：zhyiroy
