Who has never experienced oscillations issues when using an operational amplifier? Opampsare often used in a simple voltage follower configuration. However, this is not the bestconfiguration in terms of capacitive loading and Potential risk of oscillations.Capacitive loads have a big impact on the stability of operational amplifier-basedapplications. Several compensation methods exist to stabilize a standard op-amp. Thisapplication note describes the most common ones, which can be used in most cases.The general theory of each compensation method is explained, and based on this, specific
標(biāo)簽： 半導(dǎo)體 運(yùn)放 穩(wěn)定性
上傳時(shí)間： 2013-10-28
上傳用戶：chenbhdt
Abstract: The rapid build out of today's smart grid raises a number of security questions. In this article,we review two recent well-documented security breaches and a report of a security gap. These situationsinclude a 2009 smart-meter hack in Puerto Rico; a 2012 password discovery in grid distributionequipment; and insecure storage of a private key in distribution automation equipment. For each of theseattacks, we examine the breach, the Potential threat, and secure silicon methods that, as part of acomplete security strategy, can help thwart the attacks.
標(biāo)簽： 智能電網(wǎng) 安全性
上傳時(shí)間： 2013-10-27
上傳用戶：tecman
Abstract: It may sound trite, but it is definitely true: the smart grid has the Potential to completely transform the energyindustry. However, smart meters and grid management alone will not ensure the success of the smart grid. Unliketraditional IT networks, smart grids require consideration of energy measurement and security. To completely optimize thistechnology, smart grid designs must focus on energy measurement and security. This tutorial considers the benefits ofboth energy measurement and security and how they make machine-to-machine networks different from traditional IT.
標(biāo)簽： 電能計(jì)量 安全性 智能電網(wǎng)
上傳時(shí)間： 2013-10-29
上傳用戶：皇族傳媒
Abstract: We don't expect manufacturers to produce clothes that in one size that fits everyone. In thesame way, one ESD component can't solve all issues—each application has different ESD requirements.Knowing that "one size fits all" cannot apply to power design, the power designer, or the engineering"super hero," must consider all the Potential disruptions to a steady flow of power and thenvarious waysto mitigate them. This tutorial describes voltage- and current-limiting devices and risetime reducers tomanage the power. It also points to free and low-cost software tools to help design lowpass filters, checkcapacitor self-resonance, and simulate circuits.
標(biāo)簽： 電源工程師 電路設(shè)計(jì)
上傳時(shí)間： 2013-11-18
上傳用戶：zhouxuepeng1
Abstract: Investment in smart meters and smart grid end equipment continues to grow worldwide as countriestry to make their electric delivery systems more efficient. However, as critical as the electric deliveryinfrastructure is, it is normally not secured and thus subject to attack. This article describes the concept oflife-cycle security—the idea that embedded equipment in the smart grid must have security designed into theentire life of the product, even back to the contract manufacturer. We also talk about how life-cycle securityapplies to embedded equipment in the smart grid. Potential threats are discussed, as are Potential solutionsto mitigate the risks posed by those threats.
標(biāo)簽： 智能電表 智能電網(wǎng)
上傳時(shí)間： 2014-12-24
上傳用戶：熊少鋒
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上傳時(shí)間： 2013-10-13
上傳用戶：ytulpx
What is New in C51 Version 8.18[Device Support]Added debug support for the NXP P89LPC9408 in the LPC900 EPM Emulator/Programmer.[New Supported Device]Nuvoton W681308 device.[New Supported Device]NXP P89LPC9201, P89LPC9211, P89LPC922A1, P89LPC9241, P89LPC9251, P89LPC9301, P89LPC931A1, P89LPC9331, P89LPC9341, and P89LPC9351 devices.[New Supported Device]SiLabs C8051F500, C8051F501, C8051F504, C8051F505, C8051F506, C8051F507, C8051F508, C8051F509, C8051F510, and C8051F511 devices.[ULINK2 Support]Corrected Potential deadlock on ST uPSD targets.[Device Simulation]Corrected simulation of Infineon XC800 MDU.[Device Simulation]Corrected behaviour of EXFn and TOGn on SiLabs C8051F12x/F13x devices.[Device Simulation]Added simulation for Atmel AT89C51RE2, including simulation of second UART.[Cx51 Compiler]Corrected failed initialization on far addresses when the object is located with _at_. 本資料僅供學(xué)習(xí)評(píng)估之用,請(qǐng)勿用于商業(yè)用途!請(qǐng)?jiān)趯W(xué)習(xí)評(píng)估24小時(shí)內(nèi)刪除.
上傳時(shí)間： 2013-11-01
上傳用戶：panpanpan
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
This text introduces the spirit and theory of hacking as well as the science behind it all it also provides some core techniques and tricks of hacking so you can think like a hacker, write your own hacks or thwart Potential system attacks. 譯作：《黑客入侵的藝術(shù)》，也是從朋友的寶箱中搜來的，以前層大致瀏覽過，是難得一件的好資料。
標(biāo)簽： introduces the hacking science
上傳時(shí)間： 2013-12-28
上傳用戶：離殤
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