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PrinetEdge-Part

  • DS1820 C51 子程序 (一線數(shù)據(jù)傳輸)

    //芯片資料請(qǐng)到www.elecfans.com查找 //DS1820 C51 子程序//這里以11.0592M晶體為例,不同的晶體速度可能需要調(diào)整延時(shí)的時(shí)間//sbit DQ =P2^1;//根據(jù)實(shí)際情況定義端口 typedef unsigned char byte;typedef unsigned int  word; //延時(shí)void delay(word useconds){  for(;useconds>0;useconds--);} //復(fù)位byte ow_reset(void){  byte presence;  DQ = 0; //pull DQ line low  delay(29); // leave it low for 480us  DQ = 1; // allow line to return high  delay(3); // wait for presence  presence = DQ; // get presence signal  delay(25); // wait for end of timeslot  return(presence); // presence signal returned}     // 0=presence, 1 = no part //從 1-wire 總線上讀取一個(gè)字節(jié)byte read_byte(void){  byte i;  byte value = 0;  for (i=8;i>0;i--)  {    value>>=1;    DQ = 0; // pull DQ low to start timeslot    DQ = 1; // then return high    delay(1);  //for (i=0; i<3; i++);     if(DQ)value|=0x80;    delay(6); // wait for rest of timeslot  }  return(value);} //向 1-WIRE 總線上寫一個(gè)字節(jié)void write_byte(char val){  byte i;  for (i=8; i>0; i--) // writes byte, one bit at a time  {    DQ = 0; // pull DQ low to start timeslot    DQ = val&0x01;    delay(5); // hold value for remainder of timeslot    DQ = 1;    val=val/2;  }  delay(5);} //讀取溫度char Read_Temperature(void){  union{    byte c[2];    int x;  }temp;   ow_reset();  write_byte(0xCC); // Skip ROM  write_byte(0xBE); // Read Scratch Pad  temp.c[1]=read_byte();  temp.c[0]=read_byte();  ow_reset();  write_byte(0xCC); //Skip ROM  write_byte(0x44); // Start Conversion  return temp.x/2;}

    標(biāo)簽: 1820 C51 DS 程序

    上傳時(shí)間: 2013-11-03

    上傳用戶:hongmo

  • XAPP452-Spartan-3高級(jí)配置架構(gòu)

    This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.

    標(biāo)簽: Spartan XAPP 452 架構(gòu)

    上傳時(shí)間: 2013-11-05

    上傳用戶:透明的心情

  • XAPP098 - Spartan FPGA低成本、高效率串行配置

    This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.

    標(biāo)簽: Spartan XAPP FPGA 098

    上傳時(shí)間: 2014-08-16

    上傳用戶:adada

  • WP401-FPGA設(shè)計(jì)的DO-254

    The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.

    標(biāo)簽: FPGA 401 254 WP

    上傳時(shí)間: 2013-11-12

    上傳用戶:q123321

  • CPLD和FPGA設(shè)計(jì)介紹

    Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.

    標(biāo)簽: CPLD FPGA

    上傳時(shí)間: 2013-10-29

    上傳用戶:lixqiang

  • PLD對(duì)FPGA數(shù)據(jù)加密

    SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?

    標(biāo)簽: FPGA PLD 數(shù)據(jù)加密

    上傳時(shí)間: 2013-11-06

    上傳用戶:wl9454

  • MEMS 經(jīng)典教材

    The field of microelectromechanical systems (MEMS), particularly micromachinedmechanical transducers, has been expanding over recent years, and the productioncosts of these devices continue to fall. Using materials, fabrication processes, anddesign tools originally developed for the microelectronic circuits industry, newtypes of microengineered device are evolving all the time—many offering numerousadvantages over their traditional counterparts. The electrical properties of siliconhave been well understood for many years, but it is the mechanical properties thathave been exploited in many examples of MEMS. This book may seem slightlyunusual in that it has four editors. However, since we all work together in this fieldwithin the School of Electronics and Computer Science at the University of Southampton,it seemed natural to work together on a project like this. MEMS are nowappearing as part of the syllabus for both undergraduate and postgraduate coursesat many universities, and we hope that this book will complement the teaching thatis taking place in this area.

    標(biāo)簽: MEMS 教材

    上傳時(shí)間: 2013-10-16

    上傳用戶:朗朗乾坤

  • NIOSII用戶定制指令

    With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor

    標(biāo)簽: NIOSII 用戶 定制 指令

    上傳時(shí)間: 2013-11-07

    上傳用戶:swing

  • CF卡技術(shù)資料

    The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.

    標(biāo)簽: 技術(shù)資料

    上傳時(shí)間: 2013-10-08

    上傳用戶:stewart·

  • S參數(shù)的設(shè)計(jì)與應(yīng)用

    Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計(jì)與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:

    標(biāo)簽: S參數(shù)

    上傳時(shí)間: 2013-12-19

    上傳用戶:aa54

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