SAM9261 BasicMMU Example code with ADS1.2 (163 kB) The goal of this project is to show how to use a PC100 SDRAM and the MMU to perform a rating with a 100MHz Bus Clock. The rating is based on Dhrystone 2.1. It shows the rate when I+D Caches are disabled or enabled, with or without MMU and I Cache is disable or enabled, with or without MMU.
This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
siptapi
A TAPI driver for SIP. With this TAPI driver you have a click2dial feature with any TAPI enabled application (e.g. MS Outlook) and any SIP account (e.g. freeworlddialup or iptel.org).
JTop monitors the CPU usage of all threads in a remote application
which has remote management enabled. JTop demonstrates the use of
the java.lang.management API to obtain the CPU consumption for
each thread.
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I² C™ and SPI™ ) and double asynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program memory make it ideal for instrumentation panels, TCP/IP enabled embedded applications as well as metering and industrial control and monitoring applications. While operating up to 40 MHz, it is also backward software and hardware compatible with the PIC18F8720.
