crc_table.c is for Reset seed( 0000 )
crc_table_1.c is for Reset seed( ffff)
CRC16_D8_m.v is a verilog module of byte paralle crc.
CRC16_D8_m_tb.v is the testbench file of above module.
Flex chip implementation
File: UP2FLEX
JTAG jumper settings: down, down, up, up
Input:
Reset - FLEX_PB1
Input n - FLEX_SW switches 1 to 8
Output:
Countdown - two 7-segment LEDs.
Done light - decimal point on Digit1.
Operation:
Setup the binary input n number.
Press the Reset switch.
See the countdown from n down to 0 on the 7-segment LEDs.
Done light lit when program terminates.
