中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
標簽： Implementing LVDS 522 Bus
上傳時間： 2013-10-26
上傳用戶：蘇蘇蘇蘇
本文檔說明實際建立一個CAN-bus網絡時，對網絡布線和CAN 接口的設計，對通訊電 纜和連接器的選擇，以及一些保障通訊可靠、提高抗干擾能力的經驗措施。
上傳時間： 2013-11-09
上傳用戶：AISINI005
CAN（Controller Area Network——控制器局域網）是一種由 CAN 控制器組成的高性能串行數據局域通信網絡，是國際上應用最廣泛的現場總線之一。它最早由德國 Bosch 公司于 1984 年推出，最初用于汽車內部測量與執行部件之間的數據通信。CAN-bus 總線模型符合 OSI 的 7 層結構；CAN-bus 規范已被 ISO 估計標準組織制定為國際標準。
上傳時間： 2013-11-13
上傳用戶：lvzhr
CANWiFi-600/622是為電信級應用而設計的工業級CAN轉WiFi接口卡/設配器，它內部集成了一路/兩路CAN-bus 接口、一個以太網接口、一路無線WIFI接口以及TCP/IP 協議棧，符合 IEEE802.11b/g/n 標準，具有傳輸速率高、接收靈敏度高和傳輸距離遠等特點，CANWIFI-600/622通過與 WiFi 基站設備（或無線寬帶路由器或無線AP）一起配合使用，設備可以在與其它擁有相同網絡ID的接入點間自由的漫游，通過無線WiFi把CAN網絡接入Wireless Ethernet。用戶利于它可以輕松完成CAN-bus 網絡和Wireless Ethernet的互連互通，進一步拓展CAN-bus 網絡的范圍。
上傳時間： 2015-01-02
上傳用戶：cooran
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上傳時間： 2013-11-21
上傳用戶：tian126vip
16kb/s Low Delay CELP 算法
上傳時間： 2015-01-03
上傳用戶：huangld
支持SSL v2/v3, TLS, PKCS #5, PKCS #7, PKCS #11, PKCS #12, S/MIME, X.509v3證書等安全協議或標準的開發庫編譯用到NSPR
上傳時間： 2014-01-27
上傳用戶：sammi
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標簽：
上傳時間： 2013-12-20
上傳用戶：sdq_123
功能強大的一個b/s工作站
標簽： 工作站
上傳時間： 2014-11-26
上傳用戶：hebmuljb
