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The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
標簽：
CANBUS
7356
NCV
單線
上傳時間：
2013-10-24
上傳用戶：s藍莓汁
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With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
標簽：
NIOSII
用戶
定制
指令
上傳時間：
2013-11-07
上傳用戶：swing
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The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標簽：
lpc
datasheet
2292
2294
上傳時間：
2014-12-30
上傳用戶：aysyzxzm
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We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
標簽：
LDO
線性
低壓差
穩(wěn)壓器
上傳時間：
2013-11-15
上傳用戶：努力努力再努力
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ZigBee技術(shù)是一種應(yīng)用于短距離范圍內(nèi)，低傳輸數(shù)據(jù)速率下的各種電子設(shè)備之間的無線通信技術(shù)。ZigBee名字來源于蜂群使用的賴以生存和發(fā)展的通信方式，蜜蜂通過跳ZigZag形狀的舞蹈來通知發(fā)現(xiàn)的新食物源的位置、距離和方向等信息，以此作為新一代無線通訊技術(shù)的名稱。ZigBee過去又稱為“HomeRF Lite”、“RF-EasyLink”或“FireFly”無線電技術(shù)，目前統(tǒng)一稱為ZigBee技術(shù)。 2、ZigBee技術(shù)的特點 自從馬可尼發(fā)明無線電以來，無線通信技術(shù)一直向著不斷提高數(shù)據(jù)速率和傳輸距離的方向發(fā)展。例如：廣域網(wǎng)范圍內(nèi)的第三代移動通信網(wǎng)絡(luò)（3G）目的在于提供多媒體無線服務(wù)，局域網(wǎng)范圍內(nèi)的標準從IEEE802.11的1Mbit/s到IEEE802.11g的54Mbit/s的數(shù)據(jù)速率。而當前得到廣泛研究的ZigBee技術(shù)則致力于提供一種廉價的固定、便攜或者移動設(shè)備使用的極低復(fù)雜度、成本和功耗的低速率無線通信技術(shù)。這種無線通信技術(shù)具有如下特點： 功耗低：工作模式情況下，ZigBee技術(shù)傳輸速率低，傳輸數(shù)據(jù)量很小，因此信號的收發(fā)時間很短，其次在非工作模式時，ZigBee節(jié)點處于休眠模式。設(shè)備搜索時延一般為30ms，休眠激活時延為15ms，活動設(shè)備信道接入時延為15ms。由于工作時間較短、收發(fā)信息功耗較低且采用了休眠模式，使得ZigBee節(jié)點非常省電，ZigBee節(jié)點的電池工作時間可以長達6個月到2年左右。同時，由于電池時間取決于很多因素，例如：電池種類、容量和應(yīng)用場合，ZigBee技術(shù)在協(xié)議上對電池使用也作了優(yōu)化。對于典型應(yīng)用，堿性電池可以使用數(shù)年，對于某些工作時間和總時間（工作時間+休眠時間）之比小于1%的情況，電池的壽命甚至可以超過10年。 數(shù)據(jù)傳輸可靠：ZigBee的媒體接入控制層（MAC層）采用talk-when-ready的碰撞避免機制。在這種完全確認的數(shù)據(jù)傳輸機制下，當有數(shù)據(jù)傳送需求時則立刻傳送，發(fā)送的每個數(shù)據(jù)包都必須等待接收方的確認信息，并進行確認信息回復(fù)，若沒有得到確認信息的回復(fù)就表示發(fā)生了碰撞，將再傳一次，采用這種方法可以提高系統(tǒng)信息傳輸?shù)目煽啃浴Ｍ瑫r為需要固定帶寬的通信業(yè)務(wù)預(yù)留了專用時隙，避免了發(fā)送數(shù)據(jù)時的競爭和沖突。同時ZigBee針對時延敏感的應(yīng)用做了優(yōu)化，通信時延和休眠狀態(tài)激活的時延都非常短。 網(wǎng)絡(luò)容量大：ZigBee低速率、低功耗和短距離傳輸?shù)奶攸c使它非常適宜支持簡單器件。ZigBee定義了兩種器件：全功能器件（FFD）和簡化功能器件（RFD）。對全功能器件，要求它支持所有的49個基本參數(shù)。而對簡化功能器件，在最小配置時只要求它支持38個基本參數(shù)。一個全功能器件可以與簡化功能器件和其他全功能器件通話，可以按3種方式工作，分別為：個域網(wǎng)協(xié)調(diào)器、協(xié)調(diào)器或器件。而簡化功能器件只能與全功能器件通話，僅用于非常簡單的應(yīng)用。一個ZigBee的網(wǎng)絡(luò)最多包括有255個ZigBee網(wǎng)路節(jié)點，其中一個是主控（Master）設(shè)備，其余則是從屬（Slave）設(shè)備。若是通過網(wǎng)絡(luò)協(xié)調(diào)器（Network Coordinator），整個網(wǎng)絡(luò)最多可以支持超過64000個ZigBee網(wǎng)路節(jié)點，再加上各個Network Coordinator可互相連接，整個ZigBee網(wǎng)絡(luò)節(jié)點的數(shù)目將十分可觀。 兼容性：ZigBee技術(shù)與現(xiàn)有的控制網(wǎng)絡(luò)標準無縫集成。通過網(wǎng)絡(luò)協(xié)調(diào)器（Coordinator）自動建立網(wǎng)絡(luò)，采用載波偵聽/沖突檢測（CSMA-CA）方式進行信道接入。為了可靠傳遞，還提供全握手協(xié)議。
標簽：
zigbee
上傳時間：
2013-11-24
上傳用戶：siguazgb
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Single-Ended and Differential S-Parameters
Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.
標簽：
差分電路
單端
模式
上傳時間：
2014-03-25
上傳用戶：yyyyyyyyyy
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The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
標簽：
314x
LPC
314
ARM
上傳時間：
2013-10-11
上傳用戶：yuchunhai1990
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標簽：
4300
LPC
ARM
雙核微控制器
上傳時間：
2013-10-28
上傳用戶：15501536189
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The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
標簽：
315x
LPC
315
ARM
上傳時間：
2014-01-17
上傳用戶：Altman
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3 FPGA設(shè)計流程
完整的FPGA 設(shè)計流程包括邏輯電路設(shè)計輸入、功能仿真、綜合及時序分析、實現(xiàn)、加載配置、調(diào)試。FPGA 配置就是將特定的應(yīng)用程序設(shè)計按FPGA設(shè)計流程轉(zhuǎn)化為數(shù)據(jù)位流加載到FPGA 的內(nèi)部存儲器中，實現(xiàn)特定邏輯功能的過程。由于FPGA 電路的內(nèi)部存儲器都是基于RAM 工藝的，所以當FPGA電路電源掉電后，內(nèi)部存儲器中已加載的位流數(shù)據(jù)將隨之丟失。所以，通常將設(shè)計完成的FPGA 位流數(shù)據(jù)存于外部存儲器中，每次上電自動進行FPGA電路配置加載。
4 FPGA配置原理
以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，F(xiàn)PGA的配置模式有四種方案可選擇：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通過芯片上的一組專/ 復(fù)用引腳信號完成的，主要配置功能信號如下：
(1)M0、M1、M2：下載配置模式選擇;
(2)CLK：配置時鐘信號;
(3)DONE：顯示配置狀態(tài)、控制器件啟動;
標簽：
Xilinx
FPGA
集成電路
動態(tài)老化
上傳時間：
2013-11-18
上傳用戶：oojj
