The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for Simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標簽： system-on-chip integrated designed reusable
上傳時間： 2013-12-20
上傳用戶：小眼睛LSL
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate Simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標簽： the Analyzer Compiler project
上傳時間： 2013-12-19
上傳用戶：Yukiseop
The Torque Network Library is a networking API designed to allow developers to easily add world-class multiuser Simulation capabilities to their products.
標簽： developers networking world-clas designed
上傳時間： 2014-01-16
上傳用戶：lvzhr
VHDL 關于2DFFT設計程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS Simulation result that is the same as the ModelSim Simulation result. u Pro2_2.wfc: VSS Simulation result of another test pattern can’t cause overflow situation.
標簽： scinode1 scinode details 2DFFT
上傳時間： 2014-12-02
上傳用戶：15071087253
<Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.vhd pre_norm_mul.vhd mul_24.vhd vcom serial_mul.vhd post_norm_mul.vhd pre_norm_div.vhd serial_div.vhd post_norm_div.vhd pre_norm_sqrt.vhd sqrt.vhd post_norm_sqrt.vhd comppack.vhd fpu.vhd ***For Simulation **** To run the Simulation read readme.txt in folder test_bench.
標簽： vhd post_norm_addsub pre_norm_addsub Floating
上傳時間： 2014-01-18
上傳用戶：czl10052678
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and Simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
Program to simulate Rayleigh fading using a p-th order autoregressive model AR(p) according to ％ Baddour s work: "Autoregressive modeling for fading channel Simulation"
標簽： autoregressive according simulate Rayleigh
上傳時間： 2013-12-02
上傳用戶：tb_6877751
The cable compensation system is an experiment system that performs Simulations of partial or microgravity environments on earth. It is a highly nonlinear and complex system.In this paper, a network based on the theory of the Fuzzy Cerebellum Model Articulation Controller(FCMAC) is proposed to control this cable compensation system. In FCMAC ,without appropriate learning rate, the control system based on FCMAC will become unstable or its convergence speed will become slow.In order to guarantee the convergence of tracking error, we present a new kind of optimization based on adaptive GA for selecting learning rate.Furthermore, this approach is evaluated and its performance is discussed.The Simulation results shows that performance of the FCMAC based the proposed method is stable and more effective.
標簽： system compensation Simulations experiment
上傳時間： 2015-08-26
上傳用戶：希醬大魔王
解釋綁定的原理，Distributed interactive Simulation system/High level architrcture
標簽：
上傳時間： 2015-09-06
上傳用戶：jing911003
基于FPGA的I2C總線模擬，采用verilog HDL語言編寫。- Based on the FPGA I2C main line Simulation, uses verilog the HDL language compilation.
上傳時間： 2013-12-13
上傳用戶：PresidentHuang
