Windows下讀寫硬件的工具. RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, Memory Index/Data, I/O Space, I/O Index/Data, Super I/O, Clock Generator, DIMM SPD, SMBus Device, CPU MSR Registers, ATA/ATAPI Identify Data, ACPI Tables Dump (include AML decode), Embedded Controller, USB Information and LPT Remote Access. And also an Command Window is provided to access hardware manually.
標簽： engineers firmware hardware Windows
上傳時間： 2015-07-01
上傳用戶：xc216
RW - Read & Write utility, for hardware engineers, firmware (BIOS) engineers, driver developers, QA engineers, performance test engineers, diagnostic engineers, etc., This utility access almost all the computer hardware, including PCI (PCI Express), PCI Index/Data, Memory, Memory Index/Data, I/O Space, I/O Index/Data, Super I/O, Clock Generator, DIMM SPD, SMBus Device, CPU MSR Registers, ATA/ATAPI Identify Data, ACPI Tables Dump (include AML decode), Embedded Controller, USB Information and LPT Remote Access. And also an Command Window is provided to access hardware manually. Website1: http://rw.net-forces.com/ Website2: http://home.kimo.com.tw/ckimchan.tw/ Website3: http://jacky5488.myweb.hinet.net/ For best view, please change the screen resolution to 1024 x 768 (or above) pixels.
標簽： engineers developers firmware hardware
上傳時間： 2013-12-22
上傳用戶：王楚楚
use double link list to implenment memory allocation. There won t appear maloc, new, delete, in my code. All is using freelist to find a suitable memory space.
標簽： allocation implenment double appear
上傳時間： 2013-12-31
上傳用戶：jhksyghr
this demo is to show you how to implement a generic SIR (a.k.a. particle, bootstrap, Monte Carlo) filter to estimate the hidden states of a nonlinear, non-Gaussian state space model.
標簽： a.k.a. bootstrap implement particle
上傳時間： 2014-11-10
上傳用戶：caozhizhi
This demo nstrates the use of the reversible jump MCMC simulated annealing for neural networks. This algorithm enables us to maximise the joint posterior distribution of the network parameters and the number of basis function. It performs a global search in the joint space of the parameters and number of parameters, thereby surmounting the problem of local minima. It allows the user to choose among various model selection criteria, including AIC, BIC and MDL
標簽： This reversible annealing the
上傳時間： 2015-07-19
上傳用戶：ma1301115706
空時正交編碼源程序，參考文獻： V.Tarokh,H. Jafarkhani,and A. R. Calderbank "Space-Time Codes from ％Orthogonal Designs",IEEE Trans. Inform. Theory VOL. 45,NO. 5,JULY 1
上傳時間： 2013-12-26
上傳用戶：fandeshun
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
標簽： the 20060125 project WinAVR
上傳時間： 2014-10-10
上傳用戶：yan2267246
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
describes the most common terms used in radarsystems, such as range, range resolution, Doppler frequency, and coherency. The second part of this chapter develops the radar range equation in many of its forms. This presentation includes the low PRF, high PRF,search, bistatic radar, and radar equation with jamming.
標簽： range radarsystems resolution describes
上傳時間： 2015-08-05
上傳用戶：宋桃子
reviews radar waveforms,including CW, pulsed, and LFM. High Range Resolution (HRR) waveforms and stepped frequency waveforms are also analyzed.
標簽： waveforms Resolution including and
上傳時間： 2014-01-11
上傳用戶：jiahao131
