什么是JTAG 到底什么是JTAG呢？ JTAG(Joint Test Action Group)聯(lián)合測(cè)試行動(dòng)小組)是一種國(guó)際標(biāo)準(zhǔn)測(cè)試協(xié)議（IEEE 1149.1兼容），主要用于芯片內(nèi)部測(cè)試。現(xiàn)在多數(shù)的高級(jí)器件都支持JTAG協(xié)議，如DSP、FPGA器件等。標(biāo)準(zhǔn)的JTAG接口是4線：TMS、 TCK、TDI、TDO，分別為模式選擇、時(shí)鐘、數(shù)據(jù)輸入和數(shù)據(jù)輸出線。 JTAG最初是用來(lái)對(duì)芯片進(jìn)行測(cè)試的，基本原理是在器件內(nèi)部定義一個(gè)TAP（Test Access Port�測(cè)試訪問(wèn)口）通過(guò)專用的JTAG測(cè)試工具對(duì)進(jìn)行內(nèi)部節(jié)點(diǎn)進(jìn)行測(cè)試。JTAG測(cè)試允許多個(gè)器件通過(guò)JTAG接口串聯(lián)在一起，形成一個(gè)JTAG鏈，能實(shí)現(xiàn)對(duì)各個(gè)器件分別測(cè)試。現(xiàn)在，JTAG接口還常用于實(shí)現(xiàn)ISP（In-System rogrammable�在線編程），對(duì)FLASH等器件進(jìn)行編程。 JTAG編程方式是在線編程，傳統(tǒng)生產(chǎn)流程中先對(duì)芯片進(jìn)行預(yù)編程現(xiàn)再裝到板上因此而改變，簡(jiǎn)化的流程為先固定器件到電路板上，再用JTAG編程，從而大大加快工程進(jìn)度。JTAG接口可對(duì)PSD芯片內(nèi)部的所有部件進(jìn)行編程 JTAG的一些說(shuō)明 通常所說(shuō)的JTAG大致分兩類，一類用于測(cè)試芯片的電氣特性，檢測(cè)芯片是否有問(wèn)題；一類用于Debug；一般支持JTAG的CPU內(nèi)都包含了這兩個(gè)模塊。 一個(gè)含有JTAG Debug接口模塊的CPU，只要時(shí)鐘正常，就可以通過(guò)JTAG接口訪問(wèn)CPU的內(nèi)部寄存器和掛在CPU總線上的設(shè)備，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）內(nèi)置模塊的寄存器，象UART，Timers，GPIO等等的寄存器。 上面說(shuō)的只是JTAG接口所具備的能力，要使用這些功能，還需要軟件的配合，具體實(shí)現(xiàn)的功能則由具體的軟件決定。 例如下載程序到RAM功能。了解SOC的都知道，要使用外接的RAM，需要參照SOC DataSheet的寄存器說(shuō)明，設(shè)置RAM的基地址，總線寬度，訪問(wèn)速度等等。有的SOC則還需要Remap，才能正常工作。運(yùn)行Firmware時(shí)，這些設(shè)置由Firmware的初始化程序完成。但如果使用JTAG接口，相關(guān)的寄存器可能還處在上電值，甚至?xí)r錯(cuò)誤值，RAM不能正常工作，所以下載必然要失敗。要正常使用，先要想辦法設(shè)置RAM。在ADW中，可以在Console窗口通過(guò)Let 命令設(shè)置，在AXD中可以在Console窗口通過(guò)Set命令設(shè)置。
上傳時(shí)間： 2013-10-23
上傳用戶：aeiouetla
針對(duì)使用硬件描述語(yǔ)言進(jìn)行設(shè)計(jì)存在的問(wèn)題，提出一種基于FPGA并采用DSP Builder作為設(shè)計(jì)工具的數(shù)字信號(hào)處理器設(shè)計(jì)方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設(shè)計(jì)流程，設(shè)計(jì)了一個(gè)12階FIR 低通數(shù)字濾波器，通過(guò)Quartus 時(shí)序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測(cè)試對(duì)設(shè)計(jì)進(jìn)行了驗(yàn)證。結(jié)果表明，所設(shè)計(jì)的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
標(biāo)簽： Builder FPGA DSP 數(shù)字信號(hào)處理器
上傳時(shí)間： 2013-11-17
上傳用戶：lo25643
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
針對(duì)傳統(tǒng)集成電路（ASIC）功能固定、升級(jí)困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡(jiǎn)便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語(yǔ)言編寫出源程序，在Virtex-II Pro 開(kāi)發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測(cè)試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時(shí)間： 2013-11-06
上傳用戶：liu123
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-07
上傳用戶：jasson5678
關(guān)于GL827L的資料
標(biāo)簽： Report_SSOP Test 827 102
上傳時(shí)間： 2014-01-08
上傳用戶：lz4v4
This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
標(biāo)簽： Virtex TEMAC XAPP 1023
上傳時(shí)間： 2013-11-11
上傳用戶：saharawalker
The correct answer for each test bank question is highlighted in bold. Test bank questions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.
標(biāo)簽： 半導(dǎo)體制造技術(shù) 英文 教程
上傳時(shí)間： 2014-12-31
上傳用戶：旗魚旗魚
AI :Auto-Insertion 自動(dòng)插件 AQL :acceptable quality level 允收水準(zhǔn) ATE :automatic test equipment 自動(dòng)測(cè)試 ATM :atmosphere 氣壓 BGA :ball grid array 球形矩陣
標(biāo)簽： SMT 術(shù)語(yǔ) 中英文 對(duì)比
上傳時(shí)間： 2013-11-20
上傳用戶：haoxiyizhong
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