lm75A溫度數字轉換器 FPGA讀寫實驗Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學習設計參考。LM75A 是一個使用了內置帶隙溫度傳感器和模數轉換技術的溫度數字轉換器。它也是一個溫度檢測器，可提供一個過熱檢測輸出。LM75A 包含許多數據寄存器：配置寄存器用來存儲器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊列等（在功能描述一節中有詳細描述）；溫度寄存器（Temp），用來存儲讀取的數字溫度；設定點寄存器（Tos & Thyst），用來存儲可編程的過熱關斷和滯后限制，器件通過2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個開漏輸出（OS），當溫度超過編程限制的值時該輸出有效。LM75A 有3 個可選的邏輯地址管腳，使得同一總線上可同時連接8個器件而不發生地址沖突。LM75A 可配置成不同的工作條件。它可設置成在正常工作模式下周期性地對環境溫度進行監控或進入關斷模式來將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊列和設定點限制可編程，為了激活OS 輸出，故障隊列定義了許多連續的故障。溫度寄存器通常存放著一個11 位的二進制數的補碼，用來實現0.125℃的精度。這個高精度在需要精確地測量溫度偏移或超出限制范圍的應用中非常有用。正常工作模式下，當器件上電時，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時，LM75A就可用作一個具有以上預定義溫度設定點的獨立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
上傳時間： 2021-10-27
上傳用戶：
FPGA采樣AD9238數據并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號為 AN9238，最大采樣率 65Mhz，精度為12 位。實驗中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個數字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
Multisim官方示例Multisim仿真例程基礎電路范例135例合集:Chapter 1 - RLC CircuitsChapter 2 - DiodesChapter 3 - TransistorsChapter 4 - AmplifiersChapter 5 - OpampsChapter 6 - FiltersChapter 7 - Miscellaneous CircuitsFundamental Circuits.pdf004 Parallel DC Circuits.ms10005 Series-Parrallel DC Circuit.ms10006 Current Analysis.ms10007 Millmans Theorem 1.ms10008 Millmans Theorem 2.ms10009 Kirchhoff's Current Law.ms10010 Thevenin's Theorem.ms10011 Superposition Principle.ms10012 Nortons Theorem and Source Conversion.ms10013 AC Voltage Measurement.ms10014 Frequency Response of the Series RL Network.ms10015 RL High and Low Pass Filter.ms10016 Frequency Response of the Series RC Network.ms10017 RC High and Low Pass Filter.ms10019 Center-Tapped Full-Wave Rectifier.ms10020 Bridge Rectifier.ms10021 Capacitor-Input Rectifier Filter.ms10022 Diode Clipper (Limiter).ms10023 Diode Clipper.ms10024 Diode Clamper (DC Restorer).ms10025 Diode Voltage Doubler.ms10026 Zener Diode and Voltage Regulation 1.ms10027 Zener Diode and Voltage Regulation 2.ms10028 Zener Diode and Voltage Regulation 3.ms10105 TTL Inverter.ms10107 TTL Gate.ms10109 OR Gate Circuit.ms10111 Over-Damp Circuit.ms10113 Critical-Damp Circuit.ms10115 Series RLC Circuit 1.ms10117 Clapp Oscillator.ms10119 Differential Amplifier 1.ms10121 Differential Amplifier in Common Mode.ms10123 LC Oscillator with Unity Gain Buffer.ms10125 Notch Filter.ms10127 PNP Differential Pair.ms10129 Crossover Network.ms10131 Second-Order High-Pass Chebyshev Filter.ms10133 Third-Order High-Pass Chebyshev Filter.ms10135 Fifth-Order High-Pass Filter.ms10
標簽： multisim
上傳時間： 2021-10-27
上傳用戶：trh505
This paper presents a new type of electromagnetic damper with rotating inertial mass that has been devel oped to control the vibrations of structures subjected to earthquakes. The electromagnetic inertial mass damper (EIMD) consists of a ball screw that converts axial oscillation of the rod end into rotational motion of the internal flflywheel and an electric generator that is turned by the rotation of the inner rod. The EIMD is able to generate a large inertial force created by the rotating flflywheel and a variable damping force devel oped by the electric generator. Device performance tests of reduced-scale and full-scale EIMDs were under taken to verify the basic characteristics of the damper and the validity of the derived theoretical formulae. Shaking table tests of a three-story structure with EIMDs and earthquake response analyses of a building with EIMDs were conducted to demonstrate the seismic response control performance of the EIMD. The EIMD is able to reduce story drifts as well as accelerations and surpasses conventional types of dampers in reducing acceleration responses.
標簽： electromagnetic response Seismic control using
上傳時間： 2021-11-04
上傳用戶：a1293065
FFeeaattuurreess ? Input voltage range: 2.2 to 6V ? Programmable LED Current ? Drives LEDs Up to 27V ? Switching Frequency：up to 800KHz ? Wide dimming frequency range: 20KHz~ 360 KHz ? Programmable Overvoltage Protection ? Tiny SOP8/PP Package
標簽： HX3248C
上傳時間： 2021-11-05
上傳用戶：aben
Wide 2.2V to 6V Input Voltage Range ? 0.20V FB adjustable LED drive current ? Directly drive 9 Series 1W LED at VIN>=6V ? Fixed 800KHz Switching Frequency ? Max. 3A Switching Current Capability ? Up to 92% efficiency ? Excellent line and load regulation ? EN PIN TTL shutdown capability ? Internal Optimize Power MOSFET
標簽： sc3633
上傳時間： 2021-11-05
上傳用戶：d1997wayne
2.7V to 5.5V input voltage Range? Efficiency up to 96% ? 24V Boost converter with 12A switch current Limit? 600KHz fixed Switching Frequency? Integrated soft-start? Thermal Shutdown? Under voltage Lockout? Support external LDO auxiliary power supply? 8-Pin SOP-PP PackageAPPLICATIONSPortable Audio Amplifier Power SupplyPower BankQC 2.0/Type CWireless ChargerPOS Printer Power SupplySmall Motor Power Supply
標簽： XR2981
上傳時間： 2021-11-05
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅動源碼+仿真激勵文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發執行信號 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號 input [15:0] i2c_addr , //I2C器件內地址 input [ 7:0] i2c_data_w , //I2C要寫的數據 output reg [ 7:0] i2c_data_r , //I2C讀出的數據 output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應答標志 0:應答 1:未應答 output reg scl , //I2C的SCL時鐘信號 inout sda , //I2C的SDA信號 //user interface output reg dri_clk //驅動I2C操作的驅動時鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態localparam st_sladdr = 8'b0000_0010; //發送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發送16位字地址localparam st_addr8 = 8'b0000_1000; //發送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數據(8 bit)localparam st_addr_rd = 8'b0010_0000; //發送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數據(8 bit)localparam st_stop = 8'b1000_0000; //結束I2C操作//reg definereg sda_dir ; //I2C數據(SDA)方向控制reg sda_out ; //SDA輸出信號reg st_done ; //狀態結束reg wr_flag ; //寫標志reg [ 6:0] cnt ; //計數reg [ 7:0] cur_state ; //狀態機當前狀態reg [ 7:0] next_state; //狀態機下一狀態reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數據reg [ 7:0] data_wr_t ; //I2C需寫的數據的臨時寄存reg [ 9:0] clk_cnt ; //分頻時
標簽： iic 接口 e2prom at24c64 verilog 驅動 仿真
上傳時間： 2021-11-05
上傳用戶：
使用主流buck降壓芯片設計雙軌電源Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator
標簽： 電源
上傳時間： 2021-11-07
上傳用戶：20125101110
