SFP模塊的國際標(biāo)準(zhǔn). Cooperation Agreement for Small Form-Factor Pluggable Transceivers
標(biāo)簽： Transceivers Cooperation Form-Factor Agreement
上傳時間： 2015-09-05
上傳用戶：h886166
The MAX481E, MAX483E, MAX485E, MAX487E–MAX491E, and MAX1487E are low-power Transceivers for RS-485 and RS-422 communications in harsh environments. Each driver output and receiver input is protected against ±15kV electrostatic discharge (ESD) shocks, without latchup. These parts contain one driver and one receiver. The MAX483E, MAX487E, MAX488E, and MAX489E feature reduced slewrate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, thus allowing error-free data transmission up to 250kbps. The driver slew rates of the MAX481E, MAX485E, MAX490E, MAX491E, and MAX1487E are not limited, allowing them to transmit up to 2.5Mbps.
標(biāo)簽： MAX Transceivers 485 low-power
上傳時間： 2013-12-22
上傳用戶：小寶愛考拉
ZigBee Wireless Networks and Transceivers - 2008 Year
標(biāo)簽： Transceivers Wireless Networks ZigBee
上傳時間： 2017-03-17
上傳用戶：牧羊人8920
The design and manufacturing of wireless radio frequency (RF) Transceivers has developed rapidly in recent ten yeas due to rapid development of RF integrated circuits and the evolution of high-speed digital signal processors (DSP). Such high speed signal processors, in conjunction with the development of high resolution analog to digital converters and digital to analog converters, has made it possible for RF designers to digitize higher intermediate frequencies, thus reducing the RF section and enhancing the overall performance of the RF section.
標(biāo)簽： Transceivers Wireless Digital
上傳時間： 2020-05-27
上傳用戶：shancjb
This document presents design techniques and reference circuits that power Virtex™-4 FXRocketIO™ multi-gigabit Transceivers (MGTs) operating at data rates below 3.125 Gb/s.When using multiple Transceivers, it is sometimes preferred to power them from a switchingpower supply. However, switching power supplies generate noise that affects transceiver
標(biāo)簽： RocketIO Virtex XAPP 946
上傳時間： 2013-11-18
上傳用戶：huang111
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial Transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標(biāo)簽： Base-Station Applications Single-Chip Transceiver
上傳時間： 2013-11-07
上傳用戶：songrui
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP Transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP Transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP Transceivers• Users can configure Virtex-5 GTP Transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-23
上傳用戶：leyesome
FTTx network architectureThe core technology of optical chips in the FTTx TransceiversThe core technology of optical transceiver in FTTxThe trend of Next-generation optical transceiver Technology for FTTx
標(biāo)簽： Fttx 應(yīng)用于 光模塊 核心
上傳時間： 2013-10-20
上傳用戶：yoleeson
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial Transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
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