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全新賽靈思（Xilinx）FPGA 7系列芯片精彩剖析:賽靈思的最新7系列FPGA芯片包括3個子系列，Artix-7、 Kintex-7和Virtex-7。在介紹芯片之前，先看看三個子系列芯片的介紹表，如下表1所示：
表1 全新Xilinx FPGA 7系列子系列介紹表
(1) Artix-7 FPGA系列——業(yè)界最低功耗和最低成本
通過表1我們不難得出以下結(jié)論： 與上一代 FPGA相比，其功耗降低了50%，成本削減了35%，性能提高30%，占用面積縮減了50%，賽靈思FPGA芯片在升級中，功耗和性能平衡得非常好。
標(biāo)簽：
Xilinx
FPGA
賽靈思
系列芯片
上傳時間：
2013-12-20
上傳用戶：dongbaobao
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賽靈思正式發(fā)貨全球首款異構(gòu) 3D FPGA，為 Nx100G 和 400G 線路卡解決方案帶來突破性集成能力
標(biāo)簽：
HT_Press_Pitch-Chinese-final
Virtex
上傳時間：
2013-11-14
上傳用戶：xmsmh
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本文是關(guān)于賽靈思Artix-7 FPGA 數(shù)據(jù)手冊:直流及開關(guān)特性的詳細(xì)介紹。
文章中也討論了以下問題：
1.全新 Artix-7 FPGA 系列有哪些主要功能和特性?
Artix-7 系列提供了業(yè)界最低功耗、最低成本的 FPGA，采用了小型封裝，配合Virtex 架構(gòu)增強(qiáng)技術(shù)，能滿足小型化產(chǎn)品的批量市場需求，這也正是此前 Spartan 系列 FPGA 所針對的市場領(lǐng)域。與 Spartan-6 FPGA 相比，Artix-7 器件的邏輯密度從 20K 到 355K 不等，不但使速度提升 30%，功耗減半，尺寸減小 50%，而且價格也降了 35%。
2.Artix-7 FPGA 系列支持哪些類型的應(yīng)用和終端市場?
Artix-7 FPGA 系列面向各種低成本、小型化以及低功耗的應(yīng)用，包括如便攜式超聲波醫(yī)療設(shè)備、軍用通信系統(tǒng)、高端專業(yè)/消費(fèi)類相機(jī)的 DSLR 鏡頭模塊，以及航空視頻分配系統(tǒng)等。
標(biāo)簽：
Artix
FPGA
賽靈思
數(shù)據(jù)手冊
上傳時間：
2013-11-12
上傳用戶：songyue1991
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This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
標(biāo)簽：
XAPP
PROM
694
讀取
上傳時間：
2013-10-09
上傳用戶：guojin_0704
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The exacting technological demands created byincreasing bandwidth requirements have given riseto significant advances in FPGA technology thatenable engineers to successfully incorporate highspeedI/O interfaces in their designs. One aspect ofdesign that plays an increasingly important role isthat of the FPGA package. As the interfaces get fasterand wider, choosing the right package has becomeone of the key considerations for the systemdesigner.
標(biāo)簽：
Virtex
247
WP
高級封裝
上傳時間：
2013-11-07
上傳用戶：wanghui2438
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽：
Virtex
FPGA
PCB
設(shè)計手冊
上傳時間：
2013-11-11
上傳用戶：zwei41
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The Virtex™-4 user access register (USR_ACCESS_Virtex4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_Virtex4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
標(biāo)簽：
USR_ACCESS
PowerPC
XAPP
719
上傳時間：
2013-12-23
上傳用戶：yuanwenjiao
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The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
標(biāo)簽：
PCI-X
XAPP
DIMM
708
上傳時間：
2013-11-24
上傳用戶：18707733937
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This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標(biāo)簽：
XAPP
740
AXI
互聯(lián)
上傳時間：
2013-11-23
上傳用戶：shen_dafa
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Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
標(biāo)簽：
Xilinx
FPGA
DC
輸出
上傳時間：
2013-10-22
上傳用戶：aeiouetla
