We describe and demonstrate an algorithm that takes as input an unorganized set of points fx1 xng IR3 on or near an unknown manifold M, and produces as output a simplicial surface that approximates M. Neither the topology, the presence of boundaries, nor the geometry of M are assumed to be known in advance — all are inferred automatically from the data. This problem naturally arises in a variety of practical situations such as range scanning an object from multiple view points, recovery of biological shapes from two-dimensional slices, and interactive surface sketching.
標簽： demonstrate unorganized algorithm describe
上傳時間： 2013-12-18
上傳用戶：xc216
Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset - FLEX_PB1 Input n - FLEX_SW switches 1 to 8 Output: Countdown - two 7-segment LEDs. Done light - decimal point on Digit1. Operation: Setup the binary input n number. Press the Reset switch. See the countdown from n down to 0 on the 7-segment LEDs. Done light lit when program terminates.
標簽： down implementation settings UP2FLEX
上傳時間： 2014-01-21
上傳用戶：sclyutian
WIDE工作流系統是意大利，瑞士等幾國研究的工作流系統，文檔介紹其原理和流程
上傳時間： 2016-12-18
上傳用戶：磊子226
J2ME CANVAS INPUT IN CHINESE
上傳時間： 2016-12-23
上傳用戶：yd19890720
Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs and an initial network ％ [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the ％ network with backpropagation. ％ ％ The activation functions must be either linear or tanh. The network ％ architecture is defined by the matrix NetDef consisting of two ％ rows. The first row specifies the hidden layer while the second ％ specifies the output layer. ％
標簽： back-propagation corresponding input-output algorithm
上傳時間： 2016-12-27
上傳用戶：exxxds
數值計算牛頓迭代法的matlab源程序 說明如下： ％fun----input,the part as the form of f(x) in the equation f(x)=0 ％ ini----input,sets the starting point to ini ％ err----input,sets admissible error ％ sol----output,returns the root of equation
上傳時間： 2014-01-12
上傳用戶：妄想演繹師
數值分析高斯——列主元消去法主程序 說明如下： ％ a----input,matrix of coefficient ％ b----input,right vector ％ sol----output,returns the solution of linear equation
標簽： input coefficient matrix vector
上傳時間： 2017-01-01
上傳用戶：dancnc
verilog code 16-bit carry look-ahead adder output [15:0] sum // 相加總和 output carryout // 進位 input [15:0] A_in // 輸入A input [15:0] B_in // 輸入B input carryin // 第一級進位 C0
標簽： output look-ahead carryout verilog
上傳時間： 2014-12-06
上傳用戶：ls530720646
verilog code array_multiplier output [7:0] product input [3:0] wire_x input [3:0] wire_y
標簽： input array_multiplier verilog product
上傳時間： 2014-01-04
上傳用戶：wxhwjf
verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder
標簽： input Dividend Quotient verilog
上傳時間： 2014-11-27
上傳用戶：三人用菜
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