此代碼可以實(shí)現(xiàn)以下功能 使用wordappalication 組件，代碼如下 啟動(dòng)Word時(shí)用如下代碼： begin try Wordapplication.Connect except MessageDlg(’Word may not be installed’, mtError, [mbOk], 0) Abort end Wordapplication.Visible := True WordApplication.Caption := ’Delphi automation’ end
標(biāo)簽： wordappalication 代碼
上傳時(shí)間： 2014-01-22
上傳用戶：Divine
在實(shí)際應(yīng)用中，編程者往往喜歡程序能自動(dòng)生成word說明文檔，說明程序運(yùn)行的狀況或運(yùn)行的結(jié)果；或者程序能提取數(shù)據(jù)庫的內(nèi)容生成word表格,使用戶能方便的查看和修改，打印。但是VC++中調(diào)用word的確不容易，特別是對(duì)word中各種函數(shù)的使用，本文以作者的工作經(jīng)驗(yàn)詳細(xì)介紹一下如何調(diào)用word和進(jìn)行word表格的填寫，有同樣需求的編友也可查看一下MSDN中的Automation Microsoft Office 97 and Microsoft office 2000。
標(biāo)簽： 實(shí)際應(yīng)用
上傳時(shí)間： 2015-04-10
上傳用戶：zhangjinzj
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
標(biāo)簽： system-on-chip integrated designed reusable
上傳時(shí)間： 2013-12-20
上傳用戶：小眼睛LSL
操作系統(tǒng)有所耳聞，它是微軟已推出的三種操作系統(tǒng)內(nèi)核之一，是一種實(shí)時(shí)操作系統(tǒng)。雖然它是一種實(shí)時(shí)操作系統(tǒng)，但是從96年發(fā)布v1.0到現(xiàn)在，它的主要用途都在民用領(lǐng)域，比如Pocket PC、SmartPhone、Automation。不像VxWorks，應(yīng)用于航空航天、軍事等領(lǐng)域。現(xiàn)在linux、VxWorks廠商也都看好嵌入式民用市場(chǎng)，激烈競爭在所難免。我看好Windows CE，因?yàn)槲④浽赑C領(lǐng)域?qū)嵲谔珡?qiáng)，用戶也早已熟悉了微軟的產(chǎn)品，把PC下的技術(shù)移植到嵌入式領(lǐng)域，首先在操作界面方面就占了上風(fēng)。
標(biāo)簽： 操作系統(tǒng)
上傳時(shí)間： 2013-12-31
上傳用戶：zhengzg
vb內(nèi)嵌flash應(yīng)用 Type=Exe Form=frmMain.frm Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#..\..\..\..\WINDOWS\SYSTEM\stdole2.tlb#OLE Automation Object={D27CDB6B-AE6D-11CF-96B8-444553540000}#1.0#0 SWFLASH.OCX Startup="frmMain" ExeName32="FlashTutorial.exe" Command32="" Name="FlashTutorial" HelpContextID="0" CompatibleMode="0" MajorVer=1 MinorVer=0 RevisionVer=0 AutoIncrementVer=0 ServerSupportFiles=0 VersionCompanyName="funky frog systems" CompilationType=0 OptimizationType=0 FavorPentiumPro(tm)=0 CodeViewDebugInfo=0 NoAliasing=0 BoundsCheck=0 OverflowCheck=0 FlPointCheck=0 FDIVCheck=0 UnroundedFP=0 StartMode=0 Unattended=0 Retained=0 ThreadPerObject=0 MaxNumberOfThreads=1
標(biāo)簽： 0000 000000000046 Reference 00020430
上傳時(shí)間： 2014-11-02
上傳用戶：lizhen9880
我們?cè)诰帉懗绦颍_發(fā)軟件的過程中如果能利用已有的程序的功能，那么可以大大減輕開發(fā)過程中程序員的工作量，同時(shí)達(dá)到事半功倍的效果。例如在工程中，許多軟件需要文字處理功能，雖然MFC提供了一些方法，但是具體實(shí)現(xiàn)起來既費(fèi)事，又有一定的困難，如果我們可以直接使用OFFICE提供的功能，豈不美哉！要實(shí)現(xiàn)這一目的，只需要利用微軟的ActiveX Automation技術(shù)就可以輕松實(shí)現(xiàn)。本例主要講述了自動(dòng)化的概念，并通過一個(gè)操作Word文檔的程序來幫助讀者朋友理解Visual C++編程中如何實(shí)現(xiàn)自動(dòng)化。
上傳時(shí)間： 2014-02-22
上傳用戶：xyipie
-- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn
標(biāo)簽： entity-architectures Multiplier contains complete
上傳時(shí)間： 2015-07-02
上傳用戶：2467478207
波形發(fā)生器，帶TESTBENCH， 多平臺(tái) -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn
標(biāo)簽： 波形發(fā)生器
上傳時(shí)間： 2014-01-20
上傳用戶：familiarsmile
1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
標(biāo)簽： Learn capabilities techniques different
上傳時(shí)間： 2014-01-18
上傳用戶：yxgi5
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
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