此代碼可以實(shí)現(xiàn)以下功能 使用wordappalication 組件，代碼如下 啟動(dòng)Word時(shí)用如下代碼： begin try Wordapplication.Connect except MessageDlg(’Word may not be installed’, mtError, [mbOk], 0) Abort end Wordapplication.Visible := True WordApplication.Caption := ’Delphi automation’ end
在實(shí)際應(yīng)用中，編程者往往喜歡程序能自動(dòng)生成word說明文檔，說明程序運(yùn)行的狀況或運(yùn)行的結(jié)果；或者程序能提取數(shù)據(jù)庫的內(nèi)容生成word表格,使用戶能方便的查看和修改，打印。但是VC++中調(diào)用word的確不容易，特別是對(duì)word中各種函數(shù)的使用，本文以作者的工作經(jīng)驗(yàn)詳細(xì)介紹一下如何調(diào)用word和進(jìn)行word表格的填寫，有同樣需求的編友也可查看一下MSDN中的Automation Microsoft Office 97 and Microsoft office 2000。
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
-- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
波形發(fā)生器，帶TESTBENCH，
多平臺(tái)
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
1)Learn more about the capabilities in Quartus:
2)Learn to use different design entry techniques
2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor,
Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
關(guān)于FPGA流水線設(shè)計(jì)的論文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.
