微弱信號檢測裝置 四川理工學院 劉鵬飛、梁天德、曾學明 摘要： 本設計以TI的Launch Pad為核心板，采用鎖相放大技術設計并制作了一套微弱信號檢測裝置，用以檢測在強噪聲背景下已知頻率微弱正弦波信號的幅度值，并在液晶屏上數(shù)字顯示出所測信號相應的幅度值。實驗結果顯示其抗干擾能力強，測量精度高。 關鍵詞：強噪聲；微弱信號；鎖相放大；Launch Pad Abstract: This design is based on the Launch Pad of TI core board, using a lock-in amplifier technique designed and produced a weak signal detection deviCE, to measure the known frequency sine wave signal amplitude values of the weak in the high noise background, and shows the measured signal amplitude of the corresponding value in the liquid crystal screen. Test results showed that it has high accuracy and strong anti-jamming capability. Keywords: weak signal detection; lock-in-amplifier; Launch Pad 1、引言 隨著現(xiàn)代科學技術的發(fā)展，在科研與生產(chǎn)過程中人們越來越需要從復雜高強度的噪聲中檢測出有用的微弱信號，因此對微弱信號的檢測成為當前科研的熱點。微弱信號并不意味著信號幅度小，而是指被噪聲淹沒的信號，“微弱”也僅是相對于噪聲而言的。只有在有效抑制噪聲的條件下有選擇的放大微弱信號的幅度，才能提取出有用信號。微弱信號檢測技術的應用相當廣泛，在生物醫(yī)學、光學、電學、材料科學等相關領域顯得愈發(fā)重要。 2、方案論證 針對微弱信號的檢測的方法有很多，比如濾波法、取樣積分器、鎖相放大器等。下面就針對這幾種方法做一簡要說明。 方案一：濾波法。 在大部分的檢測儀器中都要用到濾波方法對模擬信號進行一定的處理，例如隔離直流分量，改善信號波形，防止離散化時的波形混疊，克服噪聲的不利影響，提高信噪比等。常用的噪聲濾波器有：帶通、帶阻、高通、低通等。但是濾波方法檢測信號不能用于信號頻譜與噪聲頻譜重疊的情況，有其局限性。雖然可以對濾波器的通頻帶進行調節(jié)，但其噪聲抑制能力有限，同時其準確性與穩(wěn)定性將大打折扣。
上傳時間： 2013-11-04
上傳用戶：lty6899826
Recently a new technology for high voltage Power MOSFETshas been introduced – the CoolMOS™ . Based on thenew deviCE concept of charge compensation the RDS(on) areaproduct for e.g. 600V transistors has been reduced by afactor of 5. The deviCEs show no bipolar current contributionlike the well known tail current observed during the turn-offphase of IGBTs. CoolMOS™ virtually combines the lowswitching losses of a MOSFET with the on-state losses of anIGBT.
標簽： COOLMOS
上傳時間： 2013-11-14
上傳用戶：zhyiroy
Abstract: This application note presents an overview of the operational characteristics of accurate I²C real-time clocks (RTCs),including the DS3231, DS3231M, and DS3232. It focuses on general application guidelines that facilitate use of deviCE resources forpower management, I²C communication circuit configurations, and I²C characteristics relative to deviCE power-up sequences andinitializations. Additional discussions on decoupling are provided to support developing strategies for mitigating power-supply pushingof deviCE frequency.
上傳時間： 2013-11-23
上傳用戶：WMC_geophy
基于數(shù)字微鏡器件（Digital Micro-mirror deviCE，DMD）的哈達瑪變換光譜技術是一種新型的光譜成像技術，在國內很少有專門的文獻介紹[1-3]。文中先介紹了本實驗采用的哈達瑪光譜儀樣機的原理以及哈達瑪成像光譜儀優(yōu)于傳統(tǒng)模板的獨特之處，即獲得多通道高能量高信噪比的光譜數(shù)據(jù)，然后描述對采集到的數(shù)據(jù)做高信噪比，高分辨率壓縮處理，最后說明此方法實時性強、圖像失真小、實用價值高、應用范圍廣。
標簽： 哈達 變換光譜儀 壓縮系統(tǒng)
上傳時間： 2013-11-25
上傳用戶：eastimage
The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the deviCE) with a conversion time down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.
上傳時間： 2014-12-23
上傳用戶：eastimage
The MAX2691 low-noise amplifier (LNA) is designed forGPS L2 applications. Designed in Maxim’s advancedSiGe process, the deviCE achieves high gain andlow noise figure while maximizing the input-referred 1dBcompression point and the 3rd-order intercept point. TheMAX2691 provides a high gain of 17.5dB and sub 1dBnoise figure.
標簽： Amplifier Low-Noise 2691 Band
上傳時間： 2014-12-04
上傳用戶：zaocan888
模擬集成電路的設計與其說是一門技術，還不如說是一門藝術。它比數(shù)字集成電路設計需要更嚴格的分析和更豐富的直覺。嚴謹堅實的理論無疑是嚴格分析能力的基石，而設計者的實踐經(jīng)驗無疑是誕生豐富直覺的源泉。這也正足初學者對學習模擬集成電路設計感到困惑并難以駕馭的根本原因。.美國加州大學洛杉機分校(UCLA)Razavi教授憑借著他在美國多所著名大學執(zhí)教多年的豐富教學經(jīng)驗和在世界知名頂級公司(AT&T，Bell Lab，HP)卓著的研究經(jīng)歷為我們提供了這本優(yōu)秀的教材。本書自2000午出版以來得到了國內外讀者的好評和青睞，被許多國際知名大學選為教科書。同時，由于原著者在世界知名頂級公司的豐富研究經(jīng)歷，使本書也非常適合作為CMOS模擬集成電路設計或相關領域的研究人員和工程技術人員的參考書。... 本書介紹模擬CMOS集成電路的分析與設計。從直觀和嚴密的角度闡述了各種模擬電路的基本原理和概念，同時還闡述了在SOC中模擬電路設計遇到的新問題及電路技術的新發(fā)展。本書由淺入深，理論與實際結合，提供了大量現(xiàn)代工業(yè)中的設計實例。全書共18章。前10章介紹各種基本模塊和運放及其頻率響應和噪聲。第11章至第13章介紹帶隙基準、開關電容電路以及電路的非線性和失配的影響，第14、15章介紹振蕩器和鎖相環(huán)。第16章至18章介紹MOS器件的高階效應及其模型、CMOS制造工藝和混合信號電路的版圖與封裝。 1 Introduction to Analog Design 2 Basic MOS deviCE Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and deviCE Models 17 CMOS Processing Technology 18 Layout and Packaging
上傳時間： 2014-12-23
上傳用戶：杜瑩12345
【摘要】本文結合作者多年的印制板設計經(jīng)驗，著重印制板的電氣性能，從印制板穩(wěn)定性、可靠性方面，來討論多層印制板設計的基本要求。【關鍵詞】印制電路板；表面貼裝器件；高密度互連；通孔【Key words】Printed Circuit Board；Surface Mounting deviCE；High Density Interface；Via一．概述印制板（PCB－Printed Circuit Board）也叫印制電路板、印刷電路板。多層印制板，就是指兩層以上的印制板，它是由幾層絕緣基板上的連接導線和裝配焊接電子元件用的焊盤組成，既具有導通各層線路，又具有相互間絕緣的作用。隨著SMT（表面安裝技術）的不斷發(fā)展，以及新一代SMD（表面安裝器件）的不斷推出，如QFP、QFN、CSP、BGA（特別是MBGA），使電子產(chǎn)品更加智能化、小型化，因而推動了PCB工業(yè)技術的重大改革和進步。自1991年IBM公司首先成功開發(fā)出高密度多層板（SLC）以來，各國各大集團也相繼開發(fā)出各種各樣的高密度互連（HDI）微孔板。這些加工技術的迅猛發(fā)展，促使了PCB的設計已逐漸向多層、高密度布線的方向發(fā)展。多層印制板以其設計靈活、穩(wěn)定可靠的電氣性能和優(yōu)越的經(jīng)濟性能，現(xiàn)已廣泛應用于電子產(chǎn)品的生產(chǎn)制造中。下面，作者以多年設計印制板的經(jīng)驗，著重印制板的電氣性能，結合工藝要求，從印制板穩(wěn)定性、可靠性方面，來談談多層制板設計的基本要領。
上傳時間： 2013-11-19
上傳用戶：zczc
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express deviCEs located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express deviCE located “down” on the baseboard and a deviCE located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
為了實現(xiàn)直流電源的監(jiān)控，提出了一種具有USB HID數(shù)據(jù)通信功能的直流電源設計方案。詳細論述了基于STM32 USB固件庫（USB-FS deviCE library V3.3）的自定義HID類下位機的實現(xiàn)，介紹了如何在VC2010集成開發(fā)環(huán)境中編寫多線程上位機程序并運用PlotLab（一個快速信號繪圖和可視化的VCL組件）顯示實時波形，最后再以實驗開發(fā)板和PC實現(xiàn)了HID數(shù)據(jù)通信，證明了此監(jiān)控設計方案的可行性。
標簽： USB HID 數(shù)據(jù)通信 直流電源
上傳時間： 2013-10-17
上傳用戶：13162218709
