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CoolMos的原理、結構及制造

對于常規VDMOS器件結構， Rdson與BV存在矛盾關系，要想提高BV，都是從減小EPI參雜濃度著手，但是外延層又是正向電流流通的通道，EPI參雜濃度減小了，電阻必然變大，Rdson增大。所以對于普通VDMOS，兩者矛盾不可調和。但是對于COOLMOS，這個矛盾就不那么明顯了。通過設置一個深入EPI的的P區，大大提高了BV，同時對Rdson上不產生影響。為什么有了這個深入襯底的P區，就能大大提高耐壓呢？對于常規VDMOS，反向耐壓，主要靠的是N型EPI與body區界面的PN結，對于一個PN結，耐壓時主要靠的是耗盡區承受，耗盡區內的電場大小、耗盡區擴展的寬度的面積，也就是下圖中的淺綠色部分，就是承受電壓的大小。常規VDMOS，P body濃度要大于N EPI， PN結耗盡區主要向低參雜一側擴散，所以此結構下，P body區域一側，耗盡區擴展很小，基本對承壓沒有多大貢獻，承壓主要是P body－－N EPI在N型的一側區域，這個區域的電場強度是逐漸變化的，越是靠近PN結面（a圖的A結），電場強度E越大。所以形成的淺綠色面積有呈現梯形。

標簽： CoolMos 制造

上傳時間： 2013-11-11

上傳用戶：小眼睛LSL
應用筆記-校準激光驅動器POT和DAC

Abstract: A laser module designer can use a fixed resistor, mechanical pot, digital pot, or a digital-to-analogconverter (DAC) to control the laser driver's modulation and bias currents. The advantages of a programmablemethod (POT or DAC) are that the manufacturing process can be automated and digital control can be applied(e.g., to compensate for temperature). Using POTs can be a more simple approach than a DAC. There can be aslight cost advantage to using a POT, but this is usually not significant relative to other pieces of the design.Using a DAC can offer advantages, including improved linearity (translating to ease of software implementationand ability to hit the required accuracy), increased board density, a wider range of resolutions, a betteroptimization range, ease of use with a negative voltage laser driver, and unit-to-unit consistency

標簽： POT DAC 應用筆記校準

上傳時間： 2013-11-13

上傳用戶：ca05991270
高精度Delta-Sigma A/D轉換器原理及其應用

本次在線座談主要介紹TI的高精度Delta-Sigma A/D轉換器的原理及其應用，Delta-Sigma A/D轉換器在稱重儀器中，大量采用比例測量方法。

標簽： Delta-Sigma 高精度轉換器

上傳時間： 2013-10-17

上傳用戶：zhqzal1014
LTC1099半閃速8位AD轉換數字光電二極管陣列

This application note describes a Linear Technology "Half-Flash" A/D converter, the LTC1099, being connected to a 256 element line scan photodiode array. This technology adapts itself to handheld (i.e., low power) bar code readers, as well as high resolution automated machine inspection applications..

標簽： 1099 LTC 8位 AD轉換

上傳時間： 2013-11-21

上傳用戶：lchjng
DAC技術用語 (D/A Converters Defini

Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.

標簽： Converters Defini DAC

上傳時間： 2013-10-30

上傳用戶：stvnash
ADC轉換器技術用語 (A/D Converter Defi

ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

標簽： Converter Defi ADC 轉換器

上傳時間： 2013-11-12

上傳用戶：pans0ul
三極管代換手冊下載

三極管代換手冊下載前言使用說明三極管對照表 A B C D E F G H K L M …… 外形與管腳排列圖

標簽： 三極管代換手冊

上傳時間： 2013-10-24

上傳用戶：zjf3110
CV181L-A-20_Specification_V1.0(大功放）

cv181l-a-20

標簽： Specification_V 181 1.0 L-A

上傳時間： 2013-11-14

上傳用戶：daijun20803
pci e PCB設計規范

This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.

標簽： pci PCB 設計規范

上傳時間： 2013-10-15

上傳用戶：busterman
PRO/E 經典問題100例

PRO/E 經典問答100例

標簽： PRO 100

上傳時間： 2013-10-22

上傳用戶：kqc13037348641