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  • Vishay新型功率MOSFET采用反向?qū)б齌O-252DP

    Vishay新型功率MOSFET采用反向?qū)б齌O-252DPAK封裝

    標簽: Vishay MOSFET 252 DP

    上傳時間: 2013-11-09

    上傳用戶:immanuel2006

  • ADS to MDK轉(zhuǎn)換例程

    ADS to MDK 轉(zhuǎn)換例程由西安畢博制作的MDK指導(dǎo)視頻,下載后打開Realview mdk1.htm頁面即可播放,內(nèi)容包括:模擬仿真、開發(fā)環(huán)境的建立、啟動代碼概述等,是您盡快上手MDK的好工具

    標簽: ADS MDK to 轉(zhuǎn)換

    上傳時間: 2013-12-21

    上傳用戶:dalidala

  • 基于ZigBee技術(shù)的無線智能家用燃氣報警系統(tǒng)

    在研究傳統(tǒng)家用燃氣報警器的基礎(chǔ)上,以ZigBee協(xié)議為平臺,構(gòu)建mesh網(wǎng)狀網(wǎng)絡(luò)實現(xiàn)網(wǎng)絡(luò)化的智能語音報警系統(tǒng)。由于傳感器本身的溫度和實際環(huán)境溫度的影響,傳感器標定后采用軟件補償方法。為了減少系統(tǒng)費用,前端節(jié)點采用半功能節(jié)點設(shè)備,路由器和協(xié)調(diào)器采用全功能節(jié)點設(shè)備,構(gòu)建mesh網(wǎng)絡(luò)所形成的家庭內(nèi)部報警系統(tǒng),通過通用的電話接口連接到外部的公用電話網(wǎng)絡(luò),啟動語音模塊進行報警。實驗結(jié)果表明,在2.4 GHz頻率下傳輸,有墻等障礙物的情況下,節(jié)點的傳輸距離大約為35 m,能夠滿足家庭需要,且系統(tǒng)工作穩(wěn)定,但在功耗方面仍需進一步改善。 Abstract:  On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol,and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator,constructed alarm system within the family by building mesh network,connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.

    標簽: ZigBee 無線智能 報警系統(tǒng)

    上傳時間: 2013-10-30

    上傳用戶:swaylong

  • 半導(dǎo)體制造技術(shù)_英文教程

    The correct answer for each test bank question is highlighted in bold. Test bank questions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.

    標簽: 半導(dǎo)體制造技術(shù) 英文 教程

    上傳時間: 2014-12-31

    上傳用戶:旗魚旗魚

  • 基于(英蓓特)STM32V100的串口程序

    This example provides a description of how  to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow:    - BaudRate = 115200 baud      - Word Length = 8 Bits    - One Stop Bit    - No parity    - Hardware flow control enabled (RTS and CTS signals)    - Receive and transmit enabled    - USART Clock disabled    - USART CPOL: Clock is active low    - USART CPHA: Data is captured on the second edge     - USART LastBit: The clock pulse of the last data bit is not output to                      the SCLK pin

    標簽: V100 STM 100 32V

    上傳時間: 2013-10-31

    上傳用戶:yy_cn

  • mm to mil tool_mm轉(zhuǎn)mil轉(zhuǎn)換工具

    mm to mil tool,mm to mil tool_mm轉(zhuǎn)mil轉(zhuǎn)換工具

    標簽: mil tool_mm mm to

    上傳時間: 2013-10-31

    上傳用戶:515414293

  • mm to mil tool_mm轉(zhuǎn)mil轉(zhuǎn)換工具

    mm to mil tool,mm to mil tool_mm轉(zhuǎn)mil轉(zhuǎn)換工具

    標簽: mil tool_mm mm to

    上傳時間: 2013-11-14

    上傳用戶:crazyer

  • Xilinx UltraScale:新一代架構(gòu)滿足您的新一代架構(gòu)需求(EN)

      中文版詳情瀏覽:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    標簽: UltraScale Xilinx 架構(gòu)

    上傳時間: 2013-11-21

    上傳用戶:wxqman

  • 采用TüV認證的FPGA開發(fā)功能安全系統(tǒng)

    This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System

    標簽: FPGA 安全系統(tǒng)

    上傳時間: 2013-11-14

    上傳用戶:zoudejile

  • 賽靈思電機控制開發(fā)套件簡介(英文版)

      The power of programmability gives industrial automation designers a highly efficient, cost-effective alternative to traditional motor control units (MCUs)。 The parallel-processing power, fast computational speeds, and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control (FOC)。   Additionally, Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing (DSP) that can tackle compute-intensive functions such as PID Controller, Clark/Park transforms, and Space Vector PWM.   The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving, proven, motor-control reference designs. The kit also shortens the process of developing custom control capabilities, with integrated peripheral functions (Ethernet, PowerLink, and PCI® Express), a motor-control FPGA mezzanine card (FMC) with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators, and prototyping support for evaluating alternative front-end circuitry.

    標簽: 賽靈思 電機控制 開發(fā)套件 英文

    上傳時間: 2013-10-28

    上傳用戶:wujijunshi

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