詳細(xì)介紹了TLC1549系列模數(shù)轉(zhuǎn)換器的特點(diǎn)及工作原理，然后根據(jù)TLC1549的工作時(shí)序和A/D轉(zhuǎn)換原理針對實(shí)際問題編寫了詳細(xì)的匯編語言程序。
Abstract:
A basic principle and characteristic of TLC1549 analog-to-digital converter are introduced? detailedly in this article.Through engineering-oriented illustration,a microcomputer programmer base on basic principle and time sequence of TLC1549 is writted.
本文依據(jù)集成電路設(shè)計(jì)方法學(xué)，探討了一種基于標(biāo)準(zhǔn)Intel 8086 微處理器的單芯片計(jì)算機(jī)平臺的架構(gòu)。研究了其與SDRAM，8255 并行接口等外圍IP 的集成，并在對AMBA協(xié)議和8086 CPU分析的基礎(chǔ)上，采用遵從AMBA傳輸協(xié)議的系統(tǒng)總線代替?zhèn)鹘y(tǒng)的8086 CPU三總線結(jié)構(gòu)，搭建了基于8086 IP 軟核的單芯片計(jì)算機(jī)系統(tǒng)，并實(shí)現(xiàn)了FPGA 功能演示。關(guān)鍵詞：微處理器； SoC；單芯片計(jì)算機(jī)；AMBA 協(xié)議
Design of 8086 CPU Based Computer-on-a-chip System（School of Electrical Engineering and Automation, Heifei University of Technology, Hefei, 230009,China）Abstract: According to the IC design methodology, this paper discusses the design of one kind of Computer-on-a-chip system architecture, which is based on the standard Intel8086 microprocessor,investigates how to integrate the 8086 CPU and peripheral IP such as, SDRAM controller, 8255 PPI etc. Based on the analysis of the standard Intel8086 microprocessor and AMBA Specification,the Computer-on-a-chip system based on 8086 CPU which uses AMBA bus instead of traditional three-bus structure of 8086 CPU is constructed, and the FPGA hardware emulation is fulfilled.Key words: Microprocessor; SoC; Computer-on-a-chip; AMBA Specification
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
The main objective of this book is to present all the relevant informationrequired for RF and micro-wave power amplifier design includingwell-known and novel theoretical approaches and practical design techniquesas well as to suggest optimum design approaches effectively combininganalytical calculations and computer-aided design. This bookcan also be very useful for lecturing to promote the analytical way ofthinking with practical verification by making a bridge between theoryand practice of RF and microwave engineering. As it often happens, anew result is the well-forgotten old one. Therefore, the demonstrationof not only new results based on new technologies or circuit schematicsis given, but some sufficiently old ideas or approaches are also introduced,that could be very useful in modern practice or could contributeto appearance of new ideas or schematic techniques.
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
