Advances in low power electronics now allow placementof battery-powered sensors and other devices in locationsfar from the power grid. Ideally, for true grid independence,the batteries should not need replacement, but instead berecharged using locally available renewable energy, suchas solar power. This Design Note shows how to producea compact battery charger that operates from a small2-cell solar panel. A unique feature of this design is thatthe DC/DC converter uses power point control to extractmaximum power from the solar panel.
上傳時間： 2014-01-20
上傳用戶：wettetw
The LTC®4151 is a high side power monitor that includesa 12-bit ADC for measuring current and voltage, as wellas the voltage on an auxiliary input. Data is read throughthe widely used I2C interface. An unusual feature in thisdevice is its 7V to 80V operating range, allowing it to coverapplications from 12V automotive to 48V telecom.
上傳時間： 2013-10-29
上傳用戶：集美慧
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
上傳時間： 2013-10-13
上傳用戶：ytulpx
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上傳時間： 2013-11-15
上傳用戶：zouxinwang
MPLAB C30用戶指南(英文) HIGHLIGHTSThe information covered in this chapter is as follows:• About this Guide• Recommended Reading• Troubleshooting• The Microchip Web Site• Development Systems Customer Notification Service• Customer Support Document LayoutThe document layout is as follows:• Chapter 1: Compiler Overview – describes MPLAB C30, development tools andfeature set.• Chapter 2: Differences between MPLAB C30 and ANSI C – describes thedifferences between the C language supported by MPLAB C30 syntax and thestandard ANSI-89 C.• Chapter 3: Using MPLAB C30 – describes how to use the MPLAB C30 compilerfrom the command line.• Chapter 4: MPLAB C30 Runtime Environment – describes the MPLAB C30runtime model, including information on sections, initialization, memory models, thesoftware stack and much more.• Chapter 5: Data Types – describes MPLAB C30 integer, floating point and pointerdata types.• Chapter 6: Device Support Files – describes the MPLAB C30 header and registerdefinition files, as well as how to use with SFR’s.• Chapter 7: Interrupts – describes how to use interrupts.• Chapter 8: Mixing Assembly Language and C Modules – provides guidelines tousing MPLAB C30 with MPLAB ASM30 assembly language modules.
上傳時間： 2013-10-21
上傳用戶：13925096126
The HCS12X family is the successor to the HCS12family, with many additional features. One new feature isthe increased memory available to the CPU and themethods available to access it. This document focuses onthe improved memory map configuration.
上傳時間： 2013-11-13
上傳用戶：王者A
提出了一種改進的LSM-ALSM子空間模式識別方法，將LSM的旋轉策略引入ALSM，使子空間之間互不關聯的情況得到改善，提高了ALSM對相似樣本的區分能力。討論中以性能函數代替經驗函數來確定拒識規則的參數，實現了識別率、誤識率與拒識率之間的最佳平衡；通過對有限字符集的實驗結果表明，LSM-ALSM算法有效地改善了分類器的識別率和可靠性。關 鍵 詞 學習子空間; 性能函數; 散布矩陣; 最小描述長度在子空間模式識別方法中，一個線性子空間代表一個模式類別，該子空間由反映類別本質的一組特征矢量張成，分類器根據輸入樣本在各子空間上的投影長度將其歸為相應的類別。典型的子空間算法有以下三種[1, 2]：CLAFIC(Class-feature Information Compression)算法以相關矩陣的部分特征向量來構造子空間，實現了特征信息的壓縮，但對樣本的利用為一次性，不能根據分類結果進行調整和學習，對樣本信息的利用不充分；學習子空間方法(Leaning Subspace Method, LSM)通過旋轉子空間來拉大樣本所屬類別與最近鄰類別的距離，以此提高分類能力，但對樣本的訓練順序敏感，同一樣本訓練的順序不同對子空間構造的影響就不同；平均學習子空間算法(Averaged Learning Subspace Method, ALSM)是在迭代訓練過程中，用錯誤分類的樣本去調整散布矩陣，訓練結果與樣本輸入順序無關，所有樣本平均參與訓練，其不足之處是各模式的子空間之間相互獨立。針對以上問題，本文提出一種改進的子空間模式識別方法。子空間模式識別的基本原理1.1 子空間的分類規則子空間模式識別方法的每一類別由一個子空間表示，子空間分類器的基本分類規則是按矢量在各子空間上的投影長度大小，將樣本歸類到最大長度所對應的類別，在類x()iω的子空間上投影長度的平方為()211,2,,()argmax()jMTkkjpg===Σx (1)式中 函數稱為分類函數；為子空間基矢量。兩類的分類情況如圖1所示。
上傳時間： 2013-12-25
上傳用戶：熊少鋒
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時間： 2013-10-22
上傳用戶：ztj182002
The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.
上傳時間： 2013-11-08
上傳用戶：lwq11
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時間： 2013-11-07
上傳用戶：swing
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