This application note discusses a variety of approaches for interfacing analog signals to 5V powered systems. Synthesizing a "rail-to-rail" op amp and scaling techniques for A/D converters are covered. A voltage-to-frequency converter, applicable where high resolution is required, is also presented.
標(biāo)簽： 微處理器 系統(tǒng)接口
上傳時(shí)間： 2013-10-12
上傳用戶：181992417
ZigBee™ 是專為低速率傳感器和控制網(wǎng)絡(luò)設(shè)計(jì)的無(wú)線網(wǎng)絡(luò)協(xié)議。有許多應(yīng)用可從ZigBee 協(xié)議受益，其中可能的一些應(yīng)用有：建筑自動(dòng)化網(wǎng)絡(luò)、住宅安防系統(tǒng)、工業(yè)控制網(wǎng)絡(luò)、遠(yuǎn)程抄表以及PC 外設(shè)。此程序包提供的是Zigbee協(xié)義棧函數(shù)庫(kù)源代碼，它實(shí)現(xiàn)了一個(gè)與物理層 無(wú)關(guān)的應(yīng)用程序接口。 因此，無(wú)需做重大修改就可以輕松地在射頻（Radio Frequency，RF）收發(fā)器之間移植應(yīng)用程序。
標(biāo)簽： ZigBee 8482 協(xié)議 低速
上傳時(shí)間： 2014-01-16
上傳用戶：Pzj
Random Number Generators（隨機(jī)數(shù)生成）包括gaussian random number generator、uniform random number generator、low-frequency hold generator、1/f noise generator等5種隨機(jī)信號(hào)生成的c源代碼
標(biāo)簽： generator random number Generators
上傳時(shí)間： 2014-12-07
上傳用戶：edisonfather
頻率調(diào)制，It is a diffrent matlab code for frequency modulation.
上傳時(shí)間： 2015-05-30
上傳用戶：wanqunsheng
Routine mampres: To obtain amplitude response from h(exp(jw)). input parameters: h :n dimensioned complex array. the frequency response is stored in h(0) to h(n-1). n :the dimension of h and amp. fs :sampling frequency (Hz). iamp:If iamp=0: The Amplitude Res. amp(k)=abs(h(k)) If iamp=1: The Amplitude Res. amp(k)=20.*alog10(abs(h(k))). output parameters: amp :n dimensioned real array. the amplitude-frequency response is stored in amp(0) to amp(n-1). Note: this program will generate a data file "filename.dat" . in chapter 2
標(biāo)簽： dimensione parameters amplitude response
上傳時(shí)間： 2013-12-19
上傳用戶：xfbs821
Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this motion into a forward and backward whil orbits. The current function makes use of two sensors to generate a bi-directional spectrogram. The method can be extended to any time-frequency distribution ％ ％ compute the forward/backward Campbell/specgtrogram ％ ％ INPUT: ％ y (n x 2) each column is measured from a different sensor ％ /////// ％ __ ％ |s1| y(:,1) ％ |__| ％ __ ％ / \ ________|/ ％ | | | s2 |/ y(:,2) ％ \____/ --------|/ ％ ％ Fs Sampling frequnecy ％ ％ OUTPUT: ％ B spectrogram/Campbel diagram ％ x x-axis coordinate vector (time or Speed) ％ y y-axis coordinate vector (frequency [Hz])
標(biāo)簽： experience elliptical decompose important
上傳時(shí)間： 2015-06-23
上傳用戶：372825274
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
標(biāo)簽： the 20060125 project WinAVR
上傳時(shí)間： 2014-10-10
上傳用戶：yan2267246
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
describes the most common terms used in radarsystems, such as range, range resolution, Doppler frequency, and coherency. The second part of this chapter develops the radar range equation in many of its forms. This presentation includes the low PRF, high PRF,search, bistatic radar, and radar equation with jamming.
標(biāo)簽： range radarsystems resolution describes
上傳時(shí)間： 2015-08-05
上傳用戶：宋桃子
reviews radar waveforms,including CW, pulsed, and LFM. High Range Resolution (HRR) waveforms and stepped frequency waveforms are also analyzed.
標(biāo)簽： waveforms Resolution including and
上傳時(shí)間： 2014-01-11
上傳用戶：jiahao131
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