DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
*** *** *** *** *** *** *****
** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s
** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a
** PIC16C54 8-bit CMOS single chip microcomputer
** Revsied Version 2.0 (4/2/92).
**
** Part use = PIC16C54-XT/JW
** Note: 1) All timings are based on a reference crystal frequency of 2MHz
** which is equivalent to an instruction cycle time of 2 usec.
** 2) Address and literal values are read in octal unless otherwise
** specified.
We address the problem of predicting a word from previous words in a sample of text. In particular,
we discuss n-gram models based on classes of words. We also discuss several statistical algorithms
for assigning words to classes based on the frequency of their co-occurrence with other words. We
find that we are able to extract classes that have the flavor of either syntactically based groupings
or semantically based groupings, depending on the nature of the underlying statistics.
Huffman codes
In telecommunication, how do we represent a
set of messages, each with an access
frequency, by a sequence of 0’s and 1’s?
To minimize the transmission and decoding
costs, we may use short strings to represent
more frequently used messages.
This problem can by solved by using an
extended binary tree which is used in the 2-
way merging problem.
This is GPS Acquisition..by Matlab, this file performs cold start acquisition on the collected "data". It
searches for GPS signals of all satellites, which are listed in field
"acqSatelliteList" in the settings structure. Function saves code phase
and frequency of the detected signals in the "acqResults" structure.
This is GPS Matlab acquisition code. Function performs cold start acquisition on the collected "data". It
searches for GPS signals of all satellites, which are listed in field
"acqSatelliteList" in the settings structure. Function saves code phase
and frequency of the detected signals in the "acqResults" structure.
This is GPS in matlab calculatePseudoranges finds relative pseudoranges for all satellites
listed in CHANNELLIST at the specified millisecond of the processed
signal. The pseudoranges contain unknown receiver clock offset. It can be
found by the least squares position search procedure.
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation.
As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface.
Very simple, very small.
RFID, the wireless technology that has helped
millions of people around the world to protect their property and
make their workplaces safer is now in danger of being viewed as a
security risk. Ray Stanton examines the love-hate relationship
between people and Radio Frequency Identification [RFID] tags and
highlights the need for informed debate about the privacy issues the
technology raises.
