Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this motion into a forward and backward whil orbits. The current function makes use of two sensors to generate a bi-directional spectrogram. The method can be extended to any time-frequency distribution
％
％ compute the forward/backward Campbell/specgtrogram
％
％ INPUT:
％ y (n x 2) each column is measured from a different sensor
％ ///////
％ __
％ |s1| y(:,1)
％ |__|
％ __
％ / \ ________|/
％ | | | s2 |/ y(:,2)
％ \____/ --------|/
％
％ Fs Sampling frequnecy
％
％ OUTPUT:
％ B spectrogram/Campbel diagram
％ x x-axis coordinate vector (time or Speed)
％ y y-axis coordinate vector (frequency [Hz])
光學設計軟件zemax源碼：
This DLL models an nular aspheric
surface as described in:
"Annular surfaces in annular field systems"
By Jose M. Sasian
Opt. eng. 36 (12) P 3401-3401 December 1997
This surface is essentially an odd aspheric surface with an offset in the aspheric terms.
The sag is given by:
Z = (c*r*r) / (1+(1-((1+k)*c*c*r*r))^ 1/2 ) + a*(r-q)^2 + b*(r-q)^3 + c*(r-q)^4 + ...
Note the terms a, b, c, ... have units of length to the -1, -2, -3, ... power.
his project was built and tested with WinAVR-20060125.
Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!!
To build the code, just install WinAVR and run "make" from the console in echomaster and
echoslave subdirs.
"make program" will program the device if you have a AVRISP attached.
Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock
from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST!
Otherwise you wont get any clock signal to the AVR and then you can t program it or reset
the fuses!
The MC1319x has default clock output of 32kHz so you will have to set your programmer to
a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
關于FPGA流水線設計的論文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.
describes the most common terms used in radarsystems, such as range, range resolution, Doppler frequency, and coherency.
The second part of this chapter develops the radar range equation in many of its forms. This presentation includes the low PRF, high PRF,search, bistatic radar, and radar equation with jamming.
％ This program calculates radar ranges in a jamming environment. It works
％ with both Stand-off jamming and self-screening jamming for steady and Swerling type
％ targets with frequency agility, coherent integration and standard atmosphere/rain
％ attenuation
本文簡要介紹了集成電路MAX038的性能，并給出了以MAX038波形產生器為核心具有四種輸出波形的函數
信號發生器的設計方案。用這種方法設計的信號發生器具有結構簡單、成本低、體積小等特點，很好地滿足
了一般的實驗要求。
關鍵詞：集成電路 信號發生器 頻率
Abstract：The performance ofIC_MAX038 was introduced briefly in this paper．At the sa／ne time，a signal generator design making
with integrated circuit MAX038 is provided，which can produce four kinds of waveforms output．The signal generator
was of characters such as simple structur，cheap expense，small volume and SO on．The signal generator contents the
demand of general experiments very wel1．
Key words：Integrated circuit Signal generator Frequency
Octane v1.01.20
The Open Compression Toolkit for C++ .
The Open Compression Toolkit is a set of modular C++ classes and utilities for implementing and testing compression algorithms.
Simple interface and skeleton code for creating new compression algorithms.
Complete testing framework for validating and comparing new algorithms.
Support for algorithms that use external dictionaries/headers.
Utility classes and sample code for bitio, frequency counting, etc.
