Software Engineering is a discipline applied by teams to produce high-quality, large-scale, cost-effective software that satisfies the users’ needs, and can be maintained over time Software Development is a weaker term where standards, tools, processes, etc. may not be applied
標(biāo)簽： high-quality Engineering large-scale discipline
上傳時(shí)間： 2014-01-09
上傳用戶：bcjtao
not use Java API to produce two simple java implementation of a dictionary interface, LinkedListDictionary and HashDictionary, that maps a String key to an Object value
標(biāo)簽： implementation LinkedListDict dictionary interface
上傳時(shí)間： 2015-07-25
上傳用戶：黃華強(qiáng)
usb to rs232 虛擬RS232串口驅(qū)動程序
上傳時(shí)間： 2015-07-25
上傳用戶：15736969615
how to creat mouse click cool stuff check it out
標(biāo)簽： creat click check mouse
上傳時(shí)間： 2013-12-10
上傳用戶：星仔
C in a Nutshell is the perfect companion to K&R, and destined to be the most reached-for reference on your desk.
標(biāo)簽： reached-for companion the reference
上傳時(shí)間： 2015-07-26
上傳用戶：kr770906
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
標(biāo)簽： the 20060125 project WinAVR
上傳時(shí)間： 2014-10-10
上傳用戶：yan2267246
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
怎么讓一天有36個(gè)小時(shí) 作者：Jon Bischke 原文地址：How to Have a 36 Hour Day
標(biāo)簽： Bischke Have Hour Jon
上傳時(shí)間： 2015-07-26
上傳用戶：yuanyuan123
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標(biāo)簽： Information Companies document subject
上傳時(shí)間： 2014-06-18
上傳用戶：cuiyashuo
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標(biāo)簽： Information Programmer Reference subject
上傳時(shí)間： 2015-08-04
上傳用戶：hxy200501
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