Over many years, RF-MEMS have been a hot topic in research at the technology and device level. In particular, various kinds of mechanical Si-MEMS resonators and piezoelectric BAW (bulk acoustic wave) resonators have been developed. The BAW technology has made its way to commercial products for passive RF filters, in particular for duplexers in RF transceiver front ends for cellular communica- tions. Beyond their use in filters, micromachined resonators can also be used in conjunction with active devices in innovative circuits and architectures.
標簽： MEMS-based Circuits Systems and
上傳時間： 2020-06-06
上傳用戶：shancjb
function y=lagr(x0,y0,x) %x0,y0為節點 %x是插值點 n=length(x0); m=length(x); for i=1:m z=x(i); s=0.0; for k=1:n p=1.0; for j=1:n if j~=k p=p*(z-x0(j))/(x0(k)-x0(j)); end end s=p*y0(k)+s; end y(i)=s; end
標簽： lagr
上傳時間： 2020-06-09
上傳用戶：shiyc2020
Fun. We (your authors) wanted a word to describe our ultimate goal for this book, as well as a word we hope you (our reader) will use to describe it, and that’s the one we chose. There are others goals, of course, but in the end, when you’ve finished the book, we’re hoping you’ll have enjoyed the activities described in these pages. Many books use the Introduction to explain exactly what the book is about, what the reader will learn, what the reader needs (a skill or maybe an item or piece of software), and what the reader will be left with when that last page is completed. And this Introduction will do those things, but … hopefully it’ll make you excited to get started.
標簽： Adventures Arduino Station Escape Gemini from
上傳時間： 2020-06-09
上傳用戶：shancjb
I can remember buying my first electronic calculator. I was teaching a graduate level statistics course and I had to have a calculator with a square root function. Back in the late 1960s, that was a pretty high-end requirement for a calculator. I managed to purchase one at the “educational discount price” of $149.95! Now, I look down at my desk at an ATmega2560 that is half the size for less than a quarter of the cost and think of all the possibilities built into that piece of hardware. I am amazed by what has happened to everything from toasters to car engines. Who-da-thunk-it 40 years ago?
上傳時間： 2020-06-09
上傳用戶：shancjb
A kinematically redundant manipulator is a serial robotic arm that has more independently driven joints than are necessary to define the desired pose (position and orientation) of its end-effector. With this definition, any planar manipulator (a manipulator whose end-effector motion is restrained in a plane) with more than three joints is a redundant manipulator. Also, a manipulator whose end-effector can accept aspatialposeisaredundant manipulator ifithas morethan sixindependently driven joints. For example, the manipulator shown in Fig. 1.1 has two 7-DOF arms mounted on a torso with three degrees of freedom (DOFs). This provides 10 DOFs for each arm. Since the end-effector of each arm can have a spatial motion with six DOFs, the arms are redundant.
標簽： Autonomous Modeling Planning Robots Path
上傳時間： 2020-06-10
上傳用戶：shancjb
This paper presents a new type of electromagnetic damper with rotating inertial mass that has been devel oped to control the vibrations of structures subjected to earthquakes. The electromagnetic inertial mass damper (EIMD) consists of a ball screw that converts axial oscillation of the rod end into rotational motion of the internal flflywheel and an electric generator that is turned by the rotation of the inner rod. The EIMD is able to generate a large inertial force created by the rotating flflywheel and a variable damping force devel oped by the electric generator. Device performance tests of reduced-scale and full-scale EIMDs were under taken to verify the basic characteristics of the damper and the validity of the derived theoretical formulae. Shaking table tests of a three-story structure with EIMDs and earthquake response analyses of a building with EIMDs were conducted to demonstrate the seismic response control performance of the EIMD. The EIMD is able to reduce story drifts as well as accelerations and surpasses conventional types of dampers in reducing acceleration responses.
標簽： electromagnetic response Seismic control using
上傳時間： 2021-11-04
上傳用戶：a1293065
FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上傳時間： 2021-12-19
上傳用戶：20125101110
LTC2756 18位乘法串行輸入電流輸出數模轉換器DAC模塊ALTIUM原理圖+PCB文件，硬件4層板設計，大小為66mmx39mm，ALTIUM設計的工程文件，包括完整的原理圖和PCB文件，可以做為你的設計參考。 原理圖器件列表： Library Component Count : 14 Name Description ---------------------------------------------------------------------------------------------------- AD8397ARDZ Imported Capacitor CAP.,1uF,X74,10V,10%,1206 Header 10X1 2.54 Header, 100mil, 2x1_1Header, 100mil, 2x1, Tin plated, TH Header, 100mil, 3x1 Header, 100mil, 3x1, Tin plated, TH KJDZ-2 快接端子 LT1012 LT1012 LT1360 LT1360 LTC2054_1 LTC2054 LTC2756AIG LTC2756AIG LTC6244 Imported LTC6655 LTC6655 Resistor RES.,1K OHMS,5%,1/16W,0603 SMA-KE CONNECTOR, SHEILDED, END LAUNCH JACK, GOLD PLATED, FOR 0.062 PCB, EDGE MOUNTED
標簽： 數模轉換器
上傳時間： 2021-12-22
上傳用戶：
Agilent 34401A Service Guide.pdfIEC Measurement Category II includes electrical devices connected to mains at an outlet on a branch circuit. Such devices include most small appliances, test equipment, and other devices that plug into a branch outlet or socket. The 34401A may be used to make measurements with the HI and LO inputs connected to mains in such devices, or to the branch outlet itself (up to 300 VAC). However, the 34401A may not be used with its HI and LO inputs connected to mains in permanently installed electrical devices such as the main circuit-breaker panel, sub-panel disconnect boxes, or permanently wired motors. Such devices and circuits are subject to overvoltages that may exceed the protection limits of the 34401A. Note: Voltages above 300 VAC may be measured only in circuits that are isolated from mains. However, transient overvoltages are also present on circuits that are isolated from mains. The Agilent 34401A are designed to safely withstand occasional transient overvoltages up to 2500 Vpk. Do not use this equipment to measure circuits where transient overvoltages could exceed this level. Additional Notices Waste Electrical and Electronic Equipment (WEEE) Directive 2002/96/EC This product complies with the WEEE Directive (2002/96/EC) marking requirement. The affixed product label (see below) indicates that you must not discard this electrical/electronic product in domestic household waste. Product Category: With reference to the equipment types in the WEEE directive Annex 1, this product is classified as a "Monitoring and Control instrumentation" product. Do not dispose in domestic household waste. To return unwanted products, contact your local Agilent office, or see www.agilent.com/environment/product for more information. Agilent 34138A Test Lead Set The Agilent 34401A is compatible with the Agilent 34138A Test Lead Set described below. Test Lead Ratings Test Leads - 1000V, 15A Fine Tip Probe Attachments - 300V, 3A Mini Grabber Attachment - 300V, 3A SMT Grabber Attachments - 300V, 3A Operation The Fine Tip, Mini Grabber, and SMT Grabber attachments plug onto the probe end of the Test Leads. Maintenance If any portion of the Test Lead Set is worn or damaged, do not use. Replace with a new Agilent 3413
標簽： agilent
上傳時間： 2022-02-20
上傳用戶：
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標簽： RTL verilog hdl
上傳時間： 2022-03-21
上傳用戶：canderile
