ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
數字與模擬電路設計技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外，幾乎所有的電路都是由半導體組件所構成，雖然半導體組件高速、高頻化時會有EMI的困擾，不過為了充分發揮半導體組件應有的性能，電路板設計與封裝技術仍具有決定性的影響。 模擬與數字技術的融合由于IC與LSI半導體本身的高速化，同時為了使機器達到正常動作的目的，因此技術上的跨越競爭越來越激烈。雖然構成系統的電路未必有clock設計，但是毫無疑問的是系統的可靠度是建立在電子組件的選用、封裝技術、電路設計與成本，以及如何防止噪訊的產生與噪訊外漏等綜合考慮。機器小型化、高速化、多功能化使得低頻/高頻、大功率信號/小功率信號、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數字電路，經常出現在同一個高封裝密度電路板，設計者身處如此的環境必需面對前所未有的設計思維挑戰，例如高穩定性電路與吵雜(noisy)性電路為鄰時，如果未將噪訊入侵高穩定性電路的對策視為設計重點，事后反復的設計變更往往成為無解的夢魘。模擬電路與高速數字電路混合設計也是如此，假設微小模擬信號增幅后再將full scale 5V的模擬信號，利用10bit A/D轉換器轉換成數字信號，由于分割幅寬祇有4.9mV，因此要正確讀取該電壓level并非易事，結果造成10bit以上的A/D轉換器面臨無法順利運作的窘境。另一典型實例是使用示波器量測某數字電路基板兩點相隔10cm的ground電位，理論上ground電位應該是零，然而實際上卻可觀測到4.9mV數倍甚至數十倍的脈沖噪訊(pulse noise)，如果該電位差是由模擬與數字混合電路的grand所造成的話，要測得4.9 mV的信號根本是不可能的事情，也就是說為了使模擬與數字混合電路順利動作，必需在封裝與電路設計有相對的對策，尤其是數字電路switching時，ground vance noise不會入侵analogue ground的防護對策，同時還需充分檢討各電路產生的電流回路(route)與電流大小，依此結果排除各種可能的干擾因素。以上介紹的實例都是設計模擬與數字混合電路時經常遇到的瓶頸，如果是設計12bit以上A/D轉換器時，它的困難度會更加復雜。
上傳時間： 2013-11-16
上傳用戶：731140412
本文將接續介紹電源與功率電路基板，以及數字電路基板導線設計。寬帶與高頻電路基板導線設計a.輸入阻抗1MHz，平滑性(flatness)50MHz 的OP增幅器電路基板圖26 是由FET 輸入的高速OP 增幅器OPA656 構成的高輸入阻抗OP 增幅電路，它的gain取決于R1、R2，本電路圖的電路定數為2 倍。此外為改善平滑性特別追加設置可以加大噪訊gain，抑制gain-頻率特性高頻領域時峰值的R3。圖26 高輸入阻抗的寬帶OP增幅電路圖27 是高輸入阻抗OP 增幅器的電路基板圖案。降低高速OP 增幅器反相輸入端子與接地之間的浮游容量非常重要，所以本電路的浮游容量設計目標低于0.5pF。如果上述部位附著大浮游容量的話，會成為高頻領域的頻率特性產生峰值的原因，嚴重時頻率甚至會因為feedback 阻抗與浮游容量，造成feedback 信號的位相延遲，最后導致頻率特性產生波動現象。此外高輸入阻抗OP 增幅器輸入部位的浮游容量也逐漸成為問題，圖27 的電路基板圖案的非反相輸入端子部位無full ground設計，如果有外部噪訊干擾之虞時，接地可設計成網格狀(mesh)。圖28 是根據圖26 制成的OP 增幅器Gain－頻率特性測試結果，由圖可知即使接近50MHz頻率特性非常平滑，-3dB cutoff頻率大約是133MHz。
標簽： PCB
上傳時間： 2013-11-13
上傳用戶：hebanlian
We provide complete power solutions with a full lineup of power managementproducts. This brochure provides an overview of our high performance DC/DC switching regulatorcontrollers for applications including datacom, telecom, industrial, automotive, medical, avionicsand control systems. We make power design easier with our industry-leading field applicationengineering support; a broad selection of demonstration boards with schematics, layout filesand parts lists; SwitcherCAD® software for simulation, application notes and comprehensivetechnical documentation.
上傳時間： 2013-10-15
上傳用戶：lz4v4
Power over Ethernet (PoE) is a new development thatallows for the delivery of power to Ethernet-based devicesvia standard Ethernet CAT5 cable, precluding the need forwall adapters or other external power sources. The PoEspecification defines a hardware detection protocol wherePower Sourcing Equipment (PSE) is able to identify PoEPowered Devices (PDs), thus allowing full backwardscompatibility with non-PoE-aware (legacy) Ethernetdevices.
上傳時間： 2013-11-11
上傳用戶：daoyue
Piezoelectric motors are used in digital cameras for autofocus,zooming and optical image stabilization. Theyare relatively small, lightweight and effi cient, but theyalso require a complicated driving scheme. Traditionally,this challenge has been met with the use ofseparatecircuits, including a step-up converter and an oversizedgeneric full-bridge drive IC. The resulting high componentcount and large board space are especially problematicin the design of cameras for ever shrinking cell phones.The LT®3572 solves these problems by combining astep-up regulator and a dual full-bridge driver in a 4mm× 4mm QFN package. Figure 1 shows a typical LT3572Piezo motor drive circuit. A step-up converter is usedto generate 30V from a low voltage power source suchas a Li-Ion battery or any input power source within thepart’s wide input voltage range of 2.7V to 10V. The highoutput voltage of the step-up converter, adjustable upto 40V, is available for the drivers at the VOUT pin. Thedrivers operate in a full-bridge fashion, where the OUTAand OUTB pins are the same polarity as the PWMA andPWMB pins, respectively, and the OUTA and OUTB pinsare inverted from PWMA and PWMB, respectively. Thestep-up converter and both Piezo drivers have their ownshutdown control. Figure 2 shows a typical layout
上傳時間： 2013-11-18
上傳用戶：hulee
Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission.
標簽： 數字電源
上傳時間： 2013-10-16
上傳用戶：dddddd
Features: High efficiency, high reliability, low cost AC input range selected by switch 100% full load burn-in test Protections: Short circuit / Over load Fixed switching frequency at 25KHz Cooling by free air convection 1 year warranty Dimensions: 199*98*38mm (L*W*H)
標簽： Switchin Output Single SKS
上傳時間： 2013-10-30
上傳用戶：taa123456
Keil C51是美國Keil Software公司出品的51系列兼容單片機C語言軟件開發系統，與匯編相比，C語言在功能上、結構性、可讀性、可維護性上有明顯的優勢，因而易學易用。Keil提供了包括C編譯器、宏匯編、連接器、庫管理和一個功能強大的仿真調試器等在內的完整開發方案，通過一個集成開發環境（uVision）將這些部分組合在一起。運行Keil軟件需要WIN98、NT、WIN2000、WINXP等操作系統。如果你使用C語言編程，那么Keil幾乎就是你的不二之選，即使不使用C語言而僅用匯編語言編程，其方便易用的集成環境、強大的軟件仿真調試工具也會令你事半功倍。 解壓縮以后安裝，步驟如下： 1.打開up51v706a.txt(本文件)記下安裝序列號。進入setup目錄點擊setup.exe進行安裝； 2.選擇Install Support....全新安裝，以前沒有安裝過或者放棄以前的序列號安裝; 選擇Update Current Installation升級安裝，將可以保持原來的序列號，不必再次輸入 3.選擇Full安裝，Next->Yes(接受版權信息)->選擇安裝目錄->Next->輸入序列號、姓名、公司 等，除了序列號以外，都隨意，可以如實輸入你的姓名等。->next-> ....直到安裝完成。 注意： 1.每次安裝都必須進行這幾步，每次都需要重新寫入AddOn標識； 2.假如安裝過程中存在病毒防火墻，可能會產生xcopy錯誤使安裝失敗，此時請先 關閉病毒防火墻，然后再安裝; 3.安裝前必須退出正在運行的Keil軟件，否則也會產生xcopy錯誤使安裝失敗； 4.安裝過程中可能會出現安裝Secrity Key錯誤，點擊確定即可。 這組安裝碼可以使用keil C51軟件到2033年12月底，夠用了吧。 Ident = Y1DZKM (這個號碼已經輸入在addon目錄下的文件中，你不必理會了) SN = K1DZP-5IUSH-A01UE *************************************** 0xfd漢字補丁已經預先處理。安裝以后可以打開工程\keil\c51\examples\0xfd\ee.uv2檢驗
上傳時間： 2013-10-18
上傳用戶：takako_yang
為提高太陽能的利用率，以ATmega8單片機為控制核心，設計了一套光電跟蹤與視日運動軌跡跟蹤互補控制的雙軸太陽跟蹤器。該跟蹤器在晴天時，利用光敏電阻采集光強判斷太陽位置,控制步進電機實現光電跟蹤；在陰天時，采集時鐘器件PCF8583的時間信息,計算當前太陽位置來實現視日運動軌跡跟蹤。實驗表明：該太陽跟蹤器能在不同天氣狀況下對太陽進行較準確地跟蹤，能量接收效率提高了30%，達到充分利用太陽能的目的。 Abstract: To improve the utilization rate of solar energy，a kind of solar tracking controller which effectively combined the sun angle tracking and photo electric tracking based on ATmega8is designed.In the sunny days，the solar tracking con-troller determines the sun's position by using photosensitive resistances to collect light intensity and control stepper motors to achieve photo electric tracking，n cloudy days，it collects clock chip PCF8583time information to calculate the current position of the sun and achieve the sun angle tracking.Experimental results show the solar tracking controller accurately tracks the sun in different weather conditions，improves received energy efficiency by30%and reaches the purpose of full use of solar energy.
上傳時間： 2013-10-15
上傳用戶：urgdil
