The Art of Computer Programming（Vol.1 fundamental Algorithms）
標(biāo)簽： Programming fundamental Algorithms Computer
上傳時間： 2013-11-28
上傳用戶：爺?shù)臍赓|(zhì)
RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
標(biāo)簽： using fundamental the RS_latch
上傳時間： 2017-07-30
上傳用戶：努力努力再努力
While faster processors, larger memory, and powerful graphics are fundamental requirements for workstations, users are also demanding a low-cost, solution-based approach wrapped around a standards-based technology. The Sun UltraTM 20 Workstation, which leverages the AMD OpteronTM processor with Direct Connect Architecture based on AMD64 technology, provides multiple operating system choices and leading nVidia graphics, delivers a platform that offers flexibility and performance in a cost-effective package with solutions to benefit customers across the board.
標(biāo)簽： requirements fundamental processors graphics
上傳時間： 2017-08-17
上傳用戶：zhaiye
fundamental to advance image processing: basic image, multiscale, and 3D representation based alot on random variables and neighborhood operation
標(biāo)簽： image representation fundamental processing
上傳時間： 2017-08-24
上傳用戶：標(biāo)點(diǎn)符號
an ofdm turorial. The tutorial introduce the describtion and fundamental of ofdm technique
標(biāo)簽： ofdm describtion fundamental introduce
上傳時間： 2017-09-13
上傳用戶：asasasas
fundamental of automation. A good book for automatic engineer. the book introduces the materials from easy to higher level.
標(biāo)簽： book fundamental automation introduces
上傳時間： 2013-12-24
上傳用戶：1583060504
Abstract—In the future communication applications, users may obtain their messages that have different importance levels distributively from several available sources, such as distributed storage or even devices belonging to other users. This scenario is the best modeled by the multilevel diversity coding systems (MDCS). To achieve perfect (information-theoretic) secrecy against wiretap channels, this paper investigates the fundamental limits on the secure rate region of the asymmetric MDCS (AMDCS), which include the symmetric case as a special case. Threshold perfect secrecy is added to the AMDCS model. The eavesdropper may have access to any one but not more than one subset of the channels but know nothing about the sources, as long as the size of the subset is not above the security level. The question of whether superposition (source separation) coding is optimal for such an AMDCS with threshold perfect secrecy is answered. A class of secure AMDCS (S-AMDCS) with an arbitrary number of encoders is solved, and it is shown that linear codes are optimal for this class of instances. However, in contrast with the secure symmetric MDCS, superposition is shown to be not optimal for S-AMDCS in general. In addition, necessary conditions on the existence of a secrecy key are determined as a design guideline.
標(biāo)簽： fundamental Limits Secure Class on of
上傳時間： 2020-01-04
上傳用戶：kddlas
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標(biāo)簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時間： 2013-11-12
上傳用戶：pans0ul
Sensing and/or controlling current flow is a fundamental requirement in many electronics systems, and the tech-niques to do so are as diverse as the applications them-selves.
標(biāo)簽： 電流采樣
上傳時間： 2013-10-15
上傳用戶：daoyue
Sensing and/or controlling current flow is a fundamental requirement in many electronics systems, and the tech-niques to do so are as diverse as the applications them-selves. This Application Note compiles solutions to cur-rent sensing problems and organizes the solutions by general application type. These circuits have been culled from a variety of Linear Technology documents
標(biāo)簽： 電流檢測電路
上傳時間： 2013-10-22
上傳用戶：moshushi0009
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