Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
標(biāo)簽： SHIFTER name module Input
上傳時間： 2014-01-20
上傳用戶：三人用菜
M3GExport enables developers to export complex 3D animated scenes from Maya® directly to Mobile 3D Graphics file format (M3G), the emerging 3D file format for mobile 3D games. Created by the developers of JBenchmark3D - the leading performance measurement tool for mobile 3D graphics, M3GExport lets use sophisticated features of M3G format like skeletal animation, morphing meshes, triangle stripping and other useful optimisations. M3GExport for Maya is available in two editions, Limited and Standard. The Standard version contains sophisticated optimisation options used mostly by commercial game developers.
標(biāo)簽： developers M3GExport animated directly
上傳時間： 2014-08-11
上傳用戶：xjz632
一篇關(guān)于TCP-Vegas的文獻(xiàn):Vegas is an implementation of TCP that achieves between 37 and 71％ better throughput on the Internet, with onefifth to one-half the losses, as compared to the implementation of TCP in the Reno distribution of BSD Unix. This paper motivates and describes the three key techniques employed by Vegas, and presents the results of a comprehensive experimental performance study—using both simulations and measurements on the Internet—of the Vegas and Reno implementations of TCP.
標(biāo)簽： implementation TCP-Vegas throughpu achieves
上傳時間： 2014-01-08
上傳用戶：lwwhust
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs.
標(biāo)簽： TMS 320 fixed-point processor
上傳時間： 2013-12-27
上傳用戶：宋桃子
螺旋槳PID控制 In response to constant pressure to design more efficient, faster, smaller, and better systems, engineers are constantly looking for ways to improve existing designs or replace them with better ones. Facing large fuel costs, the aerospace industry in particular has been researching alternative designs to increase fuel efficiency and performance. One such alternative is the development of reconfigurable aircraft wings. These wings would be able to adapt to the current environment increasing lift or reducing drag when appropriate.
標(biāo)簽： efficient response constant pressure
上傳時間： 2016-11-22
上傳用戶：trepb001
The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-performance benchmark test originally developed by Reinhold Weicker in 1984. This benchmark is used to measure and compare the performance of different computers or, in this case, the efficiency of the code generated for the same computer by different compilers. The test reports general performance in dhrystones per second. Like most benchmark programs, dhrystone consists of standard code and concentrates on string handling. It uses no floating-point operations. It is heavily influenced by hardware and software design, compiler and linker options, code optimizing, cache memory, wait states, and integer data types. The DHRY program is available in different targets: Simulator: Large Model: DHRY example in LARGE model for Simulation Philips 80C51MX: DHRY example in LARGE model for the Philips 80C51MC
標(biāo)簽： general-performanc benchmarks Dhrystone dhrystone
上傳時間： 2016-11-30
上傳用戶：hphh
MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces the MATLAB code that implements the two algorithms (i.e., Algorithms 1 and 2 in [1], or Algorithms 4.1 and 4.2 in [2]) used for the construction of quincunx filter banks with perfect reconstruction, linear phase, high coding gain, certain vanishing moments properties, and good frequency selectivity. The code can be used to design quincunx filter banks with two, three, or four lifting steps. The SeDuMi Matlab toolbox [3] is used to solve the second-order cone programming subproblems in the two algorithms, and must be installed in order for this code to work.
標(biāo)簽： introduces Quincunx Optimal MATLAB
上傳時間： 2014-01-15
上傳用戶：cc1
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
The SL74HC573 is identical in pinout to the LS/ALS573. The device inputs are compatible with standard CMOS outputs with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
標(biāo)簽： compatible The 573 identical
上傳時間： 2016-12-29
上傳用戶：變形金剛
I want to provide an example file system driver for Windows NT/2000/XP. For some time I have worked on an implementation of RomFs. RomFs is a small filesystem originally implemented in Linux, because of its simple disk layout its a good choice for an example driver. The current status is a working read-only driver that supports caching of file data, the create functionallity still needs some work but I m releasing it due to the high public demand.
標(biāo)簽： provide Windows example driver
上傳時間： 2013-12-19
上傳用戶：zsjzc
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