在汽車(chē)發(fā)動(dòng)機(jī)起動(dòng)時(shí)，若發(fā)動(dòng)機(jī)起動(dòng)后起動(dòng)機(jī)不能及時(shí)斷電，將會(huì)燒毀起動(dòng)機(jī)或損壞飛輪齒環(huán)；若變速器不在空檔位置起動(dòng)，則起動(dòng)機(jī)的瞬間動(dòng)力將使汽車(chē)位移，還可能引起交通事故和人身安全。為此介紹一種利用NXP P89LPC901單片機(jī)控制的汽車(chē)起動(dòng)保護(hù)控制器，通過(guò)檢測(cè)汽車(chē)起動(dòng)開(kāi)關(guān)、變速箱檔位、發(fā)動(dòng)機(jī)轉(zhuǎn)速，實(shí)現(xiàn)對(duì)汽車(chē)發(fā)動(dòng)機(jī)起動(dòng)過(guò)程檢測(cè)和保護(hù)。起動(dòng)保護(hù)控制器在發(fā)動(dòng)機(jī)起動(dòng)過(guò)程中通過(guò)采用逐個(gè)關(guān)閉打開(kāi)負(fù)載系統(tǒng)，解決汽車(chē)發(fā)動(dòng)機(jī)過(guò)程中因起動(dòng)電流大而對(duì)汽車(chē)電源的沖擊影響,延長(zhǎng)了電瓶壽命。 Abstract: When the automotive engine is started, the engine start motor and flywheel gear may be damaged， even traffic accidents and personal safeties may be caused by wrong operation or other factors.In order to ensure the automotive engine can be started normally and safely,it is necessary that the protecting measures and methods are considered in the automotive electrical control system.This paper introduces a kind of the automotive engine starting protect controller based on NXP P89LPC901 MCU.The controller can protect the engine starting process by detecting the starter key switch,transmission stall and engine speed.Through the use of close and open load system,the controller can solve the impact on automotive power because of the high-current load in the process of the automobile engine starting, and extend battery life.
上傳時(shí)間： 2013-10-15
上傳用戶(hù)：mikesering
針對(duì)當(dāng)前安檢力學(xué)試驗(yàn)機(jī)所能完成的試驗(yàn)種類(lèi)單一、自動(dòng)化程度低等問(wèn)題，提出一種以ATmega128單片機(jī)為核心控制器的安檢力學(xué)試驗(yàn)機(jī)的設(shè)計(jì)。詳細(xì)闡述了該安檢力學(xué)試驗(yàn)機(jī)各個(gè)組成部分的設(shè)計(jì)原理和方案，并且給出了各部分的軟件設(shè)計(jì)思想和操作流程。經(jīng)過(guò)大量測(cè)試試驗(yàn)表明：設(shè)計(jì)的安檢力學(xué)試驗(yàn)機(jī)可以完成多達(dá)十余種的力學(xué)安檢試驗(yàn)，完全符合相關(guān)國(guó)家標(biāo)準(zhǔn)，并且具有數(shù)據(jù)采集精度高、傳輸速度快、操作安全簡(jiǎn)便等特點(diǎn)，實(shí)現(xiàn)了安檢設(shè)備的多功能化、數(shù)字化和自動(dòng)化。 Abstract: Currently， many mechanical security testing machines have only one function. The degree of automation of them is low. To solve those problems， a new kind of mechanical security testing machine， using ATmega128 micro-controller as its core controller， has been advanced. It describes the components of the machine. The principles and the scheme in the designing processes are presented in detail， and the software architecture and the operation processes of each part are given. After having done many testing， we have reached the following conclusions: the mechanical security testing machine presented can do over ten mechanical security tests complying with related national standards. It has high data acquisition accuracy and high transmission speed. The operation of the machine is simple and safe. In general， this machine is a multi-functional， highly automatic， digitalized security testing device.
標(biāo)簽： ATmega 128 安檢 試驗(yàn)機(jī)
上傳時(shí)間： 2013-11-05
上傳用戶(hù)：a67818601
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶(hù)：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶(hù)：wxqman
Libnet is a cross-platform library aimed at game developers. It has an abstract high level API, which encourages developers to make their games portable across platforms and network types
標(biāo)簽： cross-platform developers abstract library
上傳時(shí)間： 2015-01-14
上傳用戶(hù)：ghostparker
High Performance MySQL (O Reilly,2004）
標(biāo)簽： Performance Reilly MySQL High
上傳時(shí)間： 2015-02-21
上傳用戶(hù)：nanfeicui
NTL is a high-performance, portable C++ library providing data structures and algorithms for manipulating signed, arbitrary length integers, and for vectors, matrices, and polynomials over the integers and over finite fields.
標(biāo)簽： high-performance algorithms structures providing
上傳時(shí)間： 2014-01-05
上傳用戶(hù)：水中浮云
SR-tree is an index structure for high-dimensional nearest neighbor queries，C++ sourcecode. SR-tree outperforms the R*-tree and the SS-tree especially for high-dimensional and non-uniform data which are likely to appear in the actual image / video applications.
標(biāo)簽： high-dimensional structure neighbor SR-tree
上傳時(shí)間： 2013-12-10
上傳用戶(hù)：zjf3110
A high quality VC++ source code implementing the very important context-based adaptive arithmetic coder.
標(biāo)簽： context-based implementing arithmetic important
上傳時(shí)間： 2015-04-10
上傳用戶(hù)：changeboy
Control of High Voltage 3-Phase BLDC Motor
標(biāo)簽： Control Voltage Phase Motor
上傳時(shí)間： 2015-04-21
上傳用戶(hù)：silenthink
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