To meet the future demand for huge traffic volume of wireless data service, the research on the fifth generation (5G) mobile communication systems has been undertaken in recent years. It is expected that the spectral and energy efficiencies in 5G mobile communication systems should be ten-fold higher than the ones in the fourth generation (4G) mobile communication systems. Therefore, it is important to further exploit the potential of spatial multiplexing of multiple antennas. In the last twenty years, multiple-input multiple-output (MIMO) antenna techniques have been considered as the key techniques to increase the capacity of wireless communication systems. When a large-scale antenna array (which is also called massive MIMO) is equipped in a base-station, or a large number of distributed antennas (which is also called large-scale distributed MIMO) are deployed, the spectral and energy efficiencies can be further improved by using spatial domain multiple access. This paper provides an overview of massive MIMO and large-scale distributed MIMO systems, including spectral efficiency analysis, channel state information (CSI) acquisition, wireless transmission technology, and resource allocation.
標(biāo)簽： Large-scale Antenna Systems
上傳時間： 2020-05-27
上傳用戶：shancjb
In order to improve the spectral efficiency in wireless communications, multiple antennas are employed at both transmitter and receiver sides, where the resulting system is referred to as the multiple-input multiple-output (MIMO) system. In MIMO systems, it is usually requiredto detect signals jointly as multiple signals are transmitted through multiple signal paths between the transmitter and the receiver. This joint detection becomes the MIMO detection.
標(biāo)簽： Complexity Detection MIMO Low
上傳時間： 2020-05-27
上傳用戶：shancjb
Use of multiple antennas at both ends of wireless links is the result of the natural progression of more than four decades of evolution of adaptive antenna technology. Recent advances have demonstrated that multiple- input-multiple-output (MIMO) wireless systems can achieve impressive increases in overall system performance.
標(biāo)簽： Technology System MIMO
上傳時間： 2020-05-28
上傳用戶：shancjb
The family of recent wireless standards included the optional employment of Multiple-Input Multiple-Output(MIMO)techniques.This was motivatedby the observationaccordingto the classic Shannon–Hartley law that the achievable channel capacity increases logarithmically with the transmit power. In contrast, the MIMO capacity increases linearly with the number of transmit antennas, provided that the number of receive antennas is equal to the number of transmit antennas. With the further proviso that the total transmit power is increased in proportion to the number of transmit antennas, a linear capacity increase is achieved upon increasing the transmit power, which justifies the spectacular success of MIMO systems.
標(biāo)簽： Multi-Functional Systems MIMO
上傳時間： 2020-05-31
上傳用戶：shancjb
The purpose of this book is to introduce the concept of the Multiple Input Multiple Output (MIMO) radio channel, which is an intelligent communication method based upon using multiple antennas. The book opens by explaining MIMO in layman’s terms to help stu- dents and people in industry working in related areas become easily familiarised with the concept. Therefore the structure of the book will be carefully arranged to allow a user to progress steadily through the chapters and understand the fundamental and mathematical principles behind MIMO through the visual and explanatory way in which they will be written. It is the intention that several references will also be provided, leading to further reading in this highly researched technology.
標(biāo)簽： Practical Guide MIMO to
上傳時間： 2020-05-31
上傳用戶：shancjb
The multiple-input multiple-output (MIMO) technique provides higher bit rates and better reliability in wireless systems. The efficient design of RF transceivers has a vital impact on the implementation of this technique. This first book is com- pletely devoted to RF transceiver design for MIMO communications. The book covers the most recent research in practical design and applications and can be an important resource for graduate students, wireless designers, and practical engineers.
標(biāo)簽： Transceiver Design RF
上傳時間： 2020-06-01
上傳用戶：shancjb
Driven by the desire to boost the quality of service of wireless systems closer to that afforded by wireline systems, space-time processing for multiple-input multiple-output (MIMO) wireless communications research has drawn remarkable interest in recent years. Excit- ing theoretical advances, complemented by rapid transition of research results to industry products and services, have created a vibrant and growing area that is already established by all counts. This offers a good opportunity to reflect on key developments in the area during the past decade and also outline emerging trends.
標(biāo)簽： Space-Time Processing
上傳時間： 2020-06-01
上傳用戶：shancjb
FPGA采樣AD9238數(shù)據(jù)并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號為 AN9238，最大采樣率 65Mhz，精度為12 位。實(shí)驗(yàn)中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個數(shù)字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實(shí)驗(yàn) Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實(shí)驗(yàn)簡介在前面的實(shí)驗(yàn)中我們練習(xí)了 SD 卡讀寫，VGA 視頻顯示等例程，本實(shí)驗(yàn)將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實(shí)驗(yàn)如果通過液晶屏顯示，需要有液晶屏模塊。2 實(shí)驗(yàn)原理在前面的實(shí)驗(yàn)中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實(shí)驗(yàn)將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠(yuǎn)遠(yuǎn)不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標(biāo)簽： fpga
上傳時間： 2021-10-27
上傳用戶：
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
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