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  • 基于FPGA設(shè)計(jì)的sdram讀寫測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明 DR

    基于FPGA設(shè)計(jì)的sdram讀寫測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明,DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時(shí)鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。timescale 1ps/1psmodule top(input                        clk,input                        rst_n,output[1:0]                  led,output                       sdram_clk,     //sdram clockoutput                       sdram_cke,     //sdram clock enableoutput                       sdram_cs_n,    //sdram chip selectoutput                       sdram_we_n,    //sdram write enableoutput                       sdram_cas_n,   //sdram column address strobeoutput                       sdram_ras_n,   //sdram row address strobeoutput[1:0]                  sdram_dqm,     //sdram data enable output[1:0]                  sdram_ba,      //sdram bank addressoutput[12:0]                 sdram_addr,    //sdram addressinout[15:0]                  sdram_dq       //sdram data);parameter MEM_DATA_BITS          = 16  ;        //external memory user interface data widthparameter ADDR_BITS              = 24  ;        //external memory user interface address widthparameter BUSRT_BITS             = 10  ;        //external memory user interface burst widthparameter BURST_SIZE             = 128 ;        //burst sizewire                             wr_burst_data_req;       // from external memory controller,write data request ,before data 1 clockwire                             wr_burst_finish;         // from external memory controller,burst write finish

    標(biāo)簽: fpga sdram verilog quartus

    上傳時(shí)間: 2021-12-18

    上傳用戶:

  • ADS8329 Verilog fpga 驅(qū)動(dòng)源碼 2.7V 至 5.5V 16 位 1MSPS 串

    ADS8329 Verilog fpga 驅(qū)動(dòng)源碼,2.7V 至 5.5V 16 位 1MSPS 串行模數(shù)轉(zhuǎn)換器 ADC芯片ADS8329數(shù)據(jù)采集的verilog代碼,已經(jīng)用在工程中,可以做為你的設(shè)計(jì)參考。( input clock,  input timer_clk_r, input reset,  output reg sample_over,  output reg ad_convn,  input ad_eocn,  output reg ad_csn,  output reg ad_clk,  input ad_dout,  output reg ad_din,  output reg [15:0] ad_data_lock);reg [15:0] ad_data_old;reg [15:0] ad_data_new;  reg [19:0] ad_data_temp; reg [15:0] ad_data;reg [4:0]  ad_data_cnt;reg [4:0]  ad_spi_cnt; reg [5:0]  time_dly_cnt;   parameter [3:0] state_mac_IDLE = 0,                state_mac_0 = 1,                state_mac_1 = 2,                state_mac_2 = 3,                state_mac_3 = 4,                state_mac_4 = 5,                state_mac_5 = 6,                state_mac_6 = 7,     state_mac_7 = 8,                state_mac_8 = 9,                state_mac_9 = 10,     state_mac_10 = 11,                state_mac_11 = 12,                state_mac_12 = 13,     state_mac_13 = 14,                state_mac_14 = 15; reg [3:0] state_curr;reg [3:0] state_next;

    標(biāo)簽: ads8329 verilog fpga 驅(qū)動(dòng)

    上傳時(shí)間: 2022-01-30

    上傳用戶:1208020161

  • AD8605/AD8606/AD8608 運(yùn)算放大器DataSheet

    Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers Data Sheet AD8605/AD8606/AD8608The AD8605, AD8606, and AD86081 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim? trimming technique, which achieves

    標(biāo)簽: 運(yùn)算放大器

    上傳時(shí)間: 2022-02-02

    上傳用戶:

  • spi 通信的master部分使用的verilog語言實(shí)現(xiàn)

    spi 通信的master部分使用的verilog語言實(shí)現(xiàn),可以做為你的設(shè)計(jì)參考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata);    input rstb,clk,mlb,start;    input [7:0] tdat;  //transmit data    input [1:0] cdiv;  //clock divider input din; output reg ss;  output reg sck;  output reg dout;     output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;

    標(biāo)簽: spi 通信 master verilog

    上傳時(shí)間: 2022-02-03

    上傳用戶:

  • PW2601_2.0.pdf規(guī)格書下載

    The PW2601 is a charger front-end integrated circuit designed to provide protection to Li-ionbatteries from failures of charging circuitry. The device monitors the input voltage, battery voltageand the charging current to make sure all three parameters are operated in normal range. Thedevice will switch off internal MOSFET to disconnect IN to OUT to protect load when any of inputvoltage, output current exceeds the threshold. The Over temperature protection (OTP) functionmonitors chip temperature to protect the device. The PW2601 also can protect the system’sbattery from being over charged by monitors the battery voltage continuously. The deviceoperates like a linear regulator, maintaining a 5.1V output with input voltages up to the input overvoltage threshold.The PW2601 is available in DFN-2x2-8L package. Standard products are Pb-free and Halogenfree

    標(biāo)簽: pw2601

    上傳時(shí)間: 2022-02-11

    上傳用戶:

  • 5G通信系統(tǒng)中massive-MIMO-FBMC技術(shù)的結(jié)合概述

    5G通信系統(tǒng)中massive-MIMO-FBMC技術(shù)的結(jié)合概述摘要為了應(yīng)對第五代移動(dòng)通信(5G)中更高數(shù)據(jù)率和更低時(shí)延的需求,大規(guī)模MIMO (massive multiple-input multiple-output)技術(shù)已經(jīng)被提出并被廣泛研究。大規(guī)模 MIMO技術(shù)能大幅度地提升多用戶網(wǎng)絡(luò)的容量。而在5G中的帶寬研究方面,特別 是針對碎片頻譜和頻譜靈活性問題,現(xiàn)有的正交頻分多址(Orthogonal Frequency Division Multiplexing, OFDM)技術(shù)不可能應(yīng)對未來的挑戰(zhàn),新的波形方案需要 被設(shè)計(jì)出來。基于此,F(xiàn)BMC(filter bank multicarrier)技術(shù)由于具有比OFDM低 得多的帶外頻譜泄露而被受到重視,并已被標(biāo)準(zhǔn)推進(jìn)組IMT-2020列為5G物理層 的主要備選方案之一。 本文首先回顧了5G中波形設(shè)計(jì)方案(主要是FBMC調(diào)制)和大規(guī)模多天線系 統(tǒng)(即massive MIMO)的現(xiàn)有工作和主要挑戰(zhàn)。然后,簡要介紹了基于Massive MIMO的FBMC系統(tǒng)中的自均衡性質(zhì),該性質(zhì)可以用于減少系統(tǒng)所需的子載波數(shù) 目。同時(shí),F(xiàn)BMC中的盲信道跟蹤性質(zhì)可以用于消除massive MIMO系統(tǒng)中的導(dǎo)頻 污染問題。盡管如此,如何將FBMC技術(shù)應(yīng)用于massive MIMO系統(tǒng)中的誤碼率、 計(jì)算復(fù)雜度、線性需求等方面仍然不明確,未來更多的研究工作需要在massive MIMO-FBMC方面展開來。 關(guān)鍵詞:大規(guī)模MIMO;FBMC;自均衡;導(dǎo)頻污染;盲均衡

    標(biāo)簽: 5G 通信系統(tǒng)

    上傳時(shí)間: 2022-02-25

    上傳用戶:

  • 一種車載充電器的設(shè)計(jì)

    以AT89S52單片機(jī)為控制核心,采用電容降壓技術(shù),Buck電路拓?fù)?PWM驅(qū)動(dòng)模塊和功率器件散熱設(shè)計(jì),通過高速的數(shù)據(jù)采集、主功率輸入輸出模塊和控制模塊,設(shè)計(jì)一種新型智能車載充電器.在充電過程中,通過負(fù)脈沖瞬間放電實(shí)現(xiàn)對鉛酸蓄電池的再生修復(fù),提高電池的有效容量,延長使用壽命.該充電器體積小、速度快、效率高、可靠性好.With AT89S52 single chip computer as the control core,a new type of intelligent car-carried charger was designed by using capacitance step-down technology,Buck circuit topology,PWM driving module and power device heat dissipation design,through high-speed data acquisition,main power input and output module and control module.In the charging process,the regeneration and repair of lead-acid batteries are realized by instantaneous discharge of negative pulse,which improves the effective capacity of batteries and prolongs their service life.The charger has the advantages of small size,fast speed,high efficiency and good reliability.

    標(biāo)簽: 車載充電器

    上傳時(shí)間: 2022-03-27

    上傳用戶:

  • 基于LabVIEW和單片機(jī)的自動(dòng)控制系統(tǒng)綜合實(shí)驗(yàn)

    設(shè)計(jì)了自動(dòng)控制系統(tǒng)綜合實(shí)驗(yàn)案例“基于LabVIEW和單片機(jī)的溫度控制系統(tǒng)設(shè)計(jì)”。實(shí)驗(yàn)系統(tǒng)硬件部分由單片機(jī)、溫度傳感器、D/A轉(zhuǎn)換模塊、調(diào)壓模塊和電烤箱組成,設(shè)計(jì)了單片機(jī)與各個(gè)模塊之間的接口電路。軟件部分采用LabVIEW軟件實(shí)現(xiàn)控制算法,并設(shè)計(jì)監(jiān)控界面實(shí)現(xiàn)參數(shù)設(shè)定、溫度數(shù)據(jù)實(shí)時(shí)監(jiān)控等功能。設(shè)計(jì)了單片機(jī)與LabVIEW軟件之間的串口通信程序,實(shí)現(xiàn)了輸入、輸出數(shù)據(jù)的傳輸。通過綜合實(shí)驗(yàn)系統(tǒng)設(shè)計(jì),使學(xué)生得到控制系統(tǒng)設(shè)計(jì)和實(shí)驗(yàn)調(diào)試等綜合能力的訓(xùn)練。A comprehensive experimental case of the automatic control system is presented,which is the design of the temperature control system based on LabVIEW and SCM.The hardware part of the experimental system is composed of the SCM,temperature sensor,D/A conversion module,voltage regulating module and electric oven.The interface circuit between the SCM and each module is designed.In the software part,LabVIEW software is used to realize the control algorithm,and the monitoring interface is designed to realize the functions of parameter setting,temperature data real-time monitoring,etc.The serial communication program between the SCM and LabVIEW software is designed to realize the transmission of input and output data.Through the design of this comprehensive experimental system,students can get the comprehensive ability training for the control system design,experiment debugging,etc.

    標(biāo)簽: labview 單片機(jī) 自動(dòng)控制系統(tǒng)

    上傳時(shí)間: 2022-03-27

    上傳用戶:qdxqdxqdxqdx

  • 1MHz換能器驅(qū)動(dòng)電路的設(shè)計(jì)

    超聲波換能器作為一種實(shí)用的檢測手段,能實(shí)現(xiàn)聲波所攜帶的信息和電能之間轉(zhuǎn)換。它的性能優(yōu)良,價(jià)格低廉,操作方便,易于調(diào)試,因此在工農(nóng)業(yè)生產(chǎn)中發(fā)揮著重要的作用。但目前換能器驅(qū)動(dòng)電路的發(fā)射頻率多為40 kHz,本文針對1 MHz的超聲波換能器電路進(jìn)行了設(shè)計(jì),主要介紹了它的發(fā)射驅(qū)動(dòng)電路和接收驅(qū)動(dòng)電路的設(shè)計(jì)方案,并對它們的功能進(jìn)行了詳細(xì)地說明。最后搭建實(shí)驗(yàn)平臺,并對電路的輸入、輸出模塊進(jìn)行了測試。實(shí)驗(yàn)結(jié)果表明,換能器電路運(yùn)行良好,可以為超聲波高精度測量領(lǐng)域的應(yīng)用提供參考。As a practical means of detection, ultrasonic transducer can realize the conversion between theinformation carried by sound wave and electric energy.It has the advantages of excellent performance,low cost, convenient operation and debugging, so plays an important role in industrial and agriculturalproduction.However, the transmitting frequency of the driving circuit for most transducer is 40 kHz.Thecircuit of 1 MHz ultrasonic transducer is designed In this paper. It mainly introduces the emissive drivingcircuit and the receiving circuit design and the detailed function of them. Finally, the experimentalplatform is built, and the circuit of input and output were tested. Experiments show that the transducer' s...

    標(biāo)簽: 換能器 驅(qū)動(dòng)電路

    上傳時(shí)間: 2022-04-28

    上傳用戶:

  • 安森美車規(guī)級1080P圖像傳感器AR0231手冊

    AR0231AT7C00XUEA0-DRBR(RGB濾光)安森美半導(dǎo)體推出采用突破性減少LED閃爍 (LFM)技術(shù)的新的230萬像素CMOS圖像傳感器樣品AR0231AT,為汽車先進(jìn)駕駛輔助系統(tǒng)(ADAS)應(yīng)用確立了一個(gè)新基準(zhǔn)。新器件能捕獲1080p高動(dòng)態(tài)范圍(HDR)視頻,還具備支持汽車安全完整性等級B(ASIL B)的特性。LFM技術(shù)(專利申請中)消除交通信號燈和汽車LED照明的高頻LED閃爍,令交通信號閱讀算法能于所有光照條件下工作。AR0231AT具有1/2.7英寸(6.82 mm)光學(xué)格式和1928(水平) x 1208(垂直)有源像素陣列。它采用最新的3.0微米背照式(BSI)像素及安森美半導(dǎo)體的DR-Pix?技術(shù),提供雙轉(zhuǎn)換增益以在所有光照條件下提升性能。它以線性、HDR或LFM模式捕獲圖像,并提供模式間的幀到幀情境切換。 AR0231AT提供達(dá)4重曝光的HDR,以出色的噪聲性能捕獲超過120dB的動(dòng)態(tài)范圍。AR0231AT能同步支持多個(gè)攝相機(jī),以易于在汽車應(yīng)用中實(shí)現(xiàn)多個(gè)傳感器節(jié)點(diǎn),和通過一個(gè)簡單的雙線串行接口實(shí)現(xiàn)用戶可編程性。它還有多個(gè)數(shù)據(jù)接口,包括MIPI(移動(dòng)產(chǎn)業(yè)處理器接口)、并行和HiSPi(高速串行像素接口)。其它關(guān)鍵特性還包括可選自動(dòng)化或用戶控制的黑電平控制,支持?jǐn)U頻時(shí)鐘輸入和提供多色濾波陣列選擇。封裝和現(xiàn)狀:AR0231AT采用11 mm x 10 mm iBGA-121封裝,現(xiàn)提供工程樣品。工作溫度范圍為-40℃至105℃(環(huán)境溫度),將完全通過AEC-Q100認(rèn)證。

    標(biāo)簽: 圖像傳感器

    上傳時(shí)間: 2022-06-27

    上傳用戶:XuVshu

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