Input The input contains blocks of 2 lines. The first line contains the number of sticks parts after cutting, there are at most 64 sticks. The second line contains the lengths of those parts separated by the space. The last line of the file contains zero. Output The output should contains the smallest possible length of original sticks, one per line. Sample Input 9 5 2 1 5 2 1 5 2 1 4 1 2 3 4 0 Sample Output 6 5
標簽： contains The blocks number
上傳時間： 2015-10-27
上傳用戶：lepoke
Input The input consists of two lines. The first line contains two integers n and k which are the lengths of the array and the sliding window. There are n integers in the second line. Output There are two lines in the output. The first line gives the minimum values in the window at each position, from left to right, respectively. The second line gives the maximum values. Sample Input 8 3 1 3 -1 -3 5 3 6 7 Sample Output -1 -3 -3 -3 3 3 3 3 5 5 6 7
上傳時間： 2014-12-21
上傳用戶：hongmo
％ because we do not truncate and shift the convolved input ％ sequence, the delay of the desired output sequence wrt ％ the convolved input sequence need only be the delay ％ introduced by the ideal weight vector centred at n=5
標簽： the convolved truncate sequence
上傳時間： 2015-12-27
上傳用戶：www240697738
This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
標簽： block-by-block acquired example streams
上傳時間： 2015-12-29
上傳用戶：bjgaofei
1) Write a function reverse(A) which takes a matrix A of arbitrary dimensions as input and returns a matrix B consisting of the columns of A in reverse order. Thus for example, if A = 1 2 3 then B = 3 2 1 4 5 6 6 5 4 7 8 9 9 8 7 Write a main program to call reverse(A) for the matrix A = magic(5). Print to the screen both A and reverse(A). 2) Write a program which accepts an input k from the keyboard, and which prints out the smallest fibonacci number that is at least as large as k. The program should also print out its position in the fibonacci sequence. Here is a sample of input and output: Enter k>0: 100 144 is the smallest fibonacci number greater than or equal to 100. It is the 12th fibonacci number.
標簽： dimensions arbitrary function reverse
上傳時間： 2016-04-16
上傳用戶：waitingfy
北京大學ACM比賽題目 Write a program to read four lines of upper case (i.e., all CAPITAL LETTERS) text input (no more than 72 characters per line) from the input file and print a vertical histogram that shows how many times each letter (but not blanks, digits, or punctuation) appears in the all-upper-case input. Format your output exactly as shown.
標簽： CAPITAL LETTERS program Write
上傳時間： 2014-01-17
上傳用戶：410805624
① 使用自動機技術實現一個詞法分析程序； ② 使用算符優先分析方法實現其語法分析程序； 需要先在運行目錄下建立一個input.txt文件，將需要分析的文法放在該文件中，分析結果，會輸出在output.txt文件中。
上傳時間： 2013-12-09
上傳用戶：stampede
This file implements a pid controller used to simulator cruise control in a car The input is a throtle value between 0 - 100 ( read on P1 ) The output is the car s speed ( P2 - P0 )
標簽： controller implements simulator control
上傳時間： 2014-01-01
上傳用戶：13160677563
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
