采用VHDL硬件描述語言設計,包含加法器,乘法器等以及寄存器的詳細設計思路和設計源碼
標簽: SOC課程設計
上傳時間: 2015-04-16
上傳用戶:kaixinyixiaxia
SOPC開發快速入門教程中文版,以非常詳細的實例來讓初學者了解基于QII和NII的FPGA/SOC的開發的基本流程,目的是為了讓初學者盡快上手。
標簽: FPGA SOC
上傳時間: 2015-10-08
上傳用戶:shzweh1234
鋰電池離線辨識方法,論文,在確定二階RC 等效電路模型的基礎上, 采用漸衰記憶的遞推最小二乘算法和擴展卡爾曼濾波算法對模型參數與 SOC 在線聯合估算。經過實驗與仿真驗證,
上傳時間: 2016-01-21
上傳用戶:zxljj3825
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: Clocking System Digital Audio Interface Analog Audio Interface Power supply Clocks, digital PLL I2C control interface 8051 MCUcontroller Audio DSP – digital audio processing 特性 Digital Audio Processor Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48)
上傳時間: 2016-05-06
上傳用戶:fagong
在鋰電池的估算中運用了卡爾曼濾波進行估算
上傳時間: 2017-05-10
上傳用戶:到底奚不奚
為了確定擬合系數運用最下二乘法進行擬合。。
標簽: SOC
上傳時間: 2017-05-10
上傳用戶:到底奚不奚
EGO1 是依元素科技基于 Xilinx Artix-7 FPGA 研發的便攜式數模混合基礎教 學平臺。EGO1 配備的 FPGA (XC7A35T-1CSG324C)具有大容量高性能等特點, 能實現較復雜的數字邏輯設計;在 FPGA 內可以構建 MicroBlaze 處理器系統, 可進行 SoC 設計。該平臺擁有豐富的外設,以及靈活的通用擴展接口。
上傳時間: 2017-10-14
上傳用戶:wlwl
1/4-inch, 5-Megapixel SOC Image Sensor Optimized for High-Volume Mobile Markets
上傳時間: 2019-09-29
上傳用戶:wsgq2019
用 verilog HDL 語言搭建一個以 ARM Cortex-M0 為處理器核的嵌入式SOC系統,系統包含以下幾個部分: (1)ARM Cortex-M0核 (2)AHB總線譯碼器 (3)AHB總線從設備多路復用器 (4)片上存儲器外設 (5)LED外設 (6)七段數碼管 (7)定時器 (8)UART
上傳時間: 2020-03-21
上傳用戶:wssss
為克服目前負載識別終端的低準確率、高復雜度、高硬件成本等弊端,該文設計了一 種基于SoC芯片RN8213B的微型化、多功能的智能電表。 闡述和應用了相似度負載識別算 法, 應用了兩光耦485通信和開關電源等技術
上傳時間: 2021-09-19
上傳用戶:13349833106