AEC-Q100 qualified ? 12 V and 24 V battery systems compliance ? 3.3 V and 5 V logic compatible I/O ? 8-channel configurable MOSFET pre-driver – High-side (N-channel and P-channel MOS) – Low-side (N-channel MOS) – H-bridge (up to 2 H-bridge) – Peak & Hold (2 loads) ? Operating battery supply voltage 3.8 V to 36 V ? Operating VDD supply voltage 4.5 V to 5.5 V ? All device pins, except the ground pins, withstand at least 40 V ? Programmable gate charge/discharge currents for improving EMI behavior
標簽： configurable Automotive pre-driver suitable channel systems MOSFET fully High side
上傳時間： 2019-03-27
上傳用戶：guaixiaolong
Texas Instruments常用元件庫 TI Analog Timer Circuit.IntLib TI logic Flip-Flop.IntLib TI logic Gate 1.IntLib TI logic Gate 2.IntLib TI logic Latch.IntLib TI logic Switch.IntLib TI Power Mgt Voltage Reference.IntLib TI Power Mgt Voltage Regulator.IntLib Texas Instruments Footprints.PcbLib等等
標簽： Instruments Texas常用元件庫 Altium Designer TI
上傳時間： 2019-11-28
上傳用戶：blue sky
The idea of writing this book arose from the need to investigate the main principles of modern power electronic control strategies, using fuzzy logic and neural networks, for research and teaching. Primarily, the book aims to be a quick learning guide for postgraduate/undergraduate students or design engineers interested in learning the fundamentals of modern control of drives and power systems in conjunction with the powerful design methodology based on VHDL.
標簽： Neural_and_Fuzzy_logic_Control
上傳時間： 2020-06-10
上傳用戶：shancjb
Artificial Intelligence (AI) is a big field, and this is a big book. We have tried to explore the full breadth of the field, which encompasses logic, probability, and continuous mathematics; perception, reasoning, learning, and action; and everything from microelectronic devices to robotic planetary explorers. The book is also big because we go into some depth. The subtitle of this book is “A Modern Approach.” The intended meaning of this rather empty phrase is that we have tried to synthesize what is now known into a common frame- work, rather than trying to explain each subfield of AI in its own historical context. We apologize to those whose subfields are, as a result, less recognizable.
標簽： A-Modern-Approach Intelligence
上傳時間： 2020-06-10
上傳用戶：shancjb
PADS logic 的用戶界面設計得非常易于使用，PADS logic 在努力滿足高級用戶需要的同時，還考慮到許多初次使用PADS 軟件的人員情況。本節教程包含以下內容：· PADS logic 中的交互操作過程· 工作空間的使用· 設置柵格(Grids)· 使用取景( Pan)和縮放(Zoom)· 常用參數的設置
標簽： pads
上傳時間： 2021-11-28
上傳用戶：
本節主要講述原理圖的繪制? 學完本節應能熟練使用PADS logic軟件繪制電路原理圖
標簽： pads
上傳時間： 2021-11-28
上傳用戶：
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標簽： RTL verilog hdl
上傳時間： 2022-03-21
上傳用戶：canderile
數字示波器功能強大,使用方便,但是價格相對昂貴。本文以Ti的MSP430F5529為主控器,以Altera公司的EP2C5T144C8 FPGA器件為邏輯控制部件設計數字示波器。模擬信號經程控放大、整形電路后形成方波信號送至FPGA測頻,根據頻率值選擇采用片上及片外高速AD分段采樣。FPGA控制片外AD采樣并將數據輸入到FIFO模塊中緩存,由單片機進行頻譜分析。測試表明:簡易示波器可以實現自動選檔、多采樣率采樣、高精度測頻及頻譜分析等功能。Digital oscilloscope is powerful and easy to use, but also expensive. The research group designed a low-cost digital oscilloscope, the chip of MSP430F5529 of TI is chosen as the main controller and the device of EP2C5T144C8 of Altera company is used as the logic control unit. Analog signal enter the programmable amplifier circuit, shaping circuit and other pre-processing circuit. The shaped rectangular wave signal is sent to FPGA for measure the frequency. According to the frequency value to select AD on-chip or off-chip high-speed AD for sampling. FPGA controls the off-chip AD sampling and buffers AD data by FIFO module. The single chip microcomputer receives the data, and do FFT for spectrum analysis. The test shows that the simple oscilloscope can realize automatic gain selection, sampling at different sampling rates, high precision frequency measurement and spectrum analysis.
上傳時間： 2022-03-27
上傳用戶：
主要內容介紹 Allegro 如何載入 Netlist，進而認識新式轉法和舊式轉法有何不同及優缺點的分析，透過本章學習可以對 Allegro 和 Capture 之間的互動關係，同時也能體驗出 Allegro 和 Capture 同步變更屬性等強大功能。Netlist 是連接線路圖和 Allegro Layout 圖檔的橋樑。在這裏所介紹的 Netlist 資料的轉入動作只是針對由 Capture（線路圖部分）產生的 Netlist 轉入 Allegro（Layout部分）1． 在 OrCAD Capture 中設計好線路圖。2． 然後由 OrCAD Capture 產生 Netlist（annotate 是在進行線路圖根據第五步產生的資料進行編改）。 3． 把產生的 Netlist 轉入 Allegro（layout 工作系統）。 4． 在 Allegro 中進行 PCB 的 layout。 5． 把在 Allegro 中產生的 back annotate（logic）轉出（在實際 layout 時可能對原有的 Netlist 有改動過），並轉入 OrCAD Capture 裏進行回編。
上傳時間： 2022-04-28
上傳用戶：kingwide
為解決移相全橋電路驅動及相角控制問題,設計了一種數字控制的移相全橋驅動電路.以TPL521為光耦隔離、IR2110為柵極驅動芯片.由DSP產生PWM信號,經過光耦隔離和邏輯電路后送至IR2110進行相角控制.文章對IR2110驅動電路原理進行分析及參數進行設計,對TMS320F28335進行設置并給出部分代碼.實驗結果表明：通過TMS320F28335可產生的不同相角的PWM波形,滿足了移相全橋對不同相角控制的要求.In order to solve the problem of phase-shifted full-bridge circuit driving and phase angle control,a digitally controlled phaseshifted full-bridge driving circuit was designed. TPL521 optocoupler isolation,IR2110 gate driver chip. PWM signals are generated by the DSP and sent to the IR2110 for phase angle control after optocoupler isolation and logic circuits. This text carries on the analysis to the principle of IR2110 drive circuit and parameter design,set up and give out some code to TMS320F28335. The experimental results show that the PWM waveforms with different phase angles generated by TMS320F28335 can meet the requirements of phase-shifted full-bridge control for different phase angles.
上傳時間： 2022-05-03
上傳用戶：zhanglei193
