此代碼是ＬＤＰＣ碼進(jìn)行BP算法的重要參考代碼，價(jià)值很高！并且可以進(jìn)行BP的改進(jìn)算法min-sum BP算法的改進(jìn)工作！參考的價(jià)值不錯(cuò)！！信道的源碼！
上傳時(shí)間： 2014-01-10
上傳用戶：luopoguixiong
The task of clustering Web sessions is to group Web sessions based on similarity and consists of maximizing the intra- group similarity while minimizing the inter-group similarity． The first and foremost question needed to be considered in clustering W b sessions is how to measure the similarity between Web sessions．However．there are many shortcomings in traditiona1 measurements．This paper introduces a new method for measuring similarities between Web pages that takes into account not only the URL but also the viewing time of the visited web page．Yhen we give a new method to measure the similarity of Web sessions using sequence alignment and the similarity of W eb page access in detail Experiments have proved that our method is valid and e幣cient．
標(biāo)簽： sessions clustering similarity Web
上傳時(shí)間： 2014-01-11
上傳用戶：songrui
在LP2900工作平臺上，利用MAX+plusII開發(fā)軟件，設(shè)計(jì)各個(gè)模塊編程實(shí)現(xiàn)基本模型計(jì)算機(jī)，其中最主要的是CPU的設(shè)計(jì)。 獨(dú)立完成運(yùn)算器的設(shè)計(jì)，并下載仿真
上傳時(shí)間： 2014-12-22
上傳用戶：15071087253
使用vriloge硬件描述語言設(shè)計(jì)數(shù)字頻率計(jì)，其對于高頻測量精確，可測范圍0—99999999HZ，在MAX+PLUSII中運(yùn)行通過并在實(shí)驗(yàn)箱上運(yùn)行通過達(dá)到要求
標(biāo)簽： vriloge 硬件描述語言 數(shù)字頻率計(jì)
上傳時(shí)間： 2016-08-29
上傳用戶：無聊來刷下
用prim算法實(shí)驗(yàn)最小生成樹 本程序中用到函數(shù)adjg( )，此函數(shù)作用是通過接受輸入的點(diǎn)數(shù)和邊數(shù)，建立無向圖。函數(shù)prg( )用于計(jì)算并輸出無向圖的鄰接矩陣。函數(shù)prim( )則用PRIM算法來尋找無向圖的最小生成樹 定義了兩個(gè)數(shù)組lowcost[max],closest[max]，若頂點(diǎn)k加入U(xiǎn)中，則令lowcost[k]=0。 定義二維數(shù)組g[ ][ ]來建立無向圖的鄰接矩陣。
標(biāo)簽： prim adjg 算法 實(shí)驗(yàn)
上傳時(shí)間： 2016-10-07
上傳用戶：tonyshao
1.把"Web"文件夾內(nèi)的文件拷貝到某個(gè)文件夾 2.在IIS中新建站點(diǎn)，指向該文件夾,如果新建虛擬路徑,會(huì)導(dǎo)致一些圖片的不正常顯示. 3."Database"文件夾內(nèi)有數(shù)據(jù)庫文件hyb2bTest_Data.MDF，在Sql Server企業(yè)管理器中選擇"附加數(shù)據(jù)庫" 4.需要修改根目錄web.config文件 <add key="DBServer" value="."/>,改成當(dāng)前數(shù)據(jù)庫地址 <add key="DBUser" value="sa"/>,改成當(dāng)前數(shù)據(jù)庫用戶名 <add key="DBPwd" value="sa"/>,改成當(dāng)前數(shù)據(jù)庫密碼 <add key="DBName" value="hyb2btest"/>,改成當(dāng)前數(shù)據(jù)庫名稱 <add key="SQLConnString" value="server=. database=hyb2btest user id=sa pwd=sa Min Pool Size=10"/>，分別也換成當(dāng)前數(shù)據(jù)庫的地址，用戶名、密碼以及數(shù)據(jù)庫名稱。 5.后臺登錄地址： 當(dāng)前路徑+manage/index.aspx 帳戶：admin 密碼：admin 環(huán)境要求： Windows2000 / Windows2003 + IIS5 + .NET Framework 1.1 + MS SQL Server 2000 或各更高版本 演示地址：www.hyb2b.cn 電話：13061363607 MSN ：huayousoft@hotmail.com
上傳時(shí)間： 2014-01-27
上傳用戶：zhliu007
// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
標(biāo)簽： Description Behavorial wb_master Filename
上傳時(shí)間： 2014-07-11
上傳用戶：zhanditian
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標(biāo)簽： bus bidirectional primarily designed
上傳時(shí)間： 2013-12-11
上傳用戶：jeffery
引入PEG（Progressive-edge-growth）算法來構(gòu)造適合線性時(shí)間編碼的LDPC校驗(yàn)矩陣，譯碼時(shí)采用簡化最小和Min-Sum譯碼算法實(shí)現(xiàn)簡化譯碼．仿真結(jié)果表明，該方法能夠構(gòu)造適合LDPC碼的線性時(shí)間編碼的下三角校驗(yàn)矩陣日，并且用此方法構(gòu)造的LDPC碼性能非常接近原來PEG算法構(gòu)造的LDPC碼．同時(shí)通過采用最小和Min-Sum算法降低譯碼復(fù)雜度．
標(biāo)簽： Progressive-edge-growth LDPC PEG 算法
上傳時(shí)間： 2013-12-27
上傳用戶：qlpqlq
采用Altera公司的FPGA芯片，在MAX+plus II軟件平臺上實(shí)現(xiàn)多路HDLC電路
上傳時(shí)間： 2016-11-13
上傳用戶：zhyiroy
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