The MC68HC05K0 is a low cost, low pin countsingle chip microcomputer with 504 bytes of userROM and 32 bytes of RAM. The MC68HC05K0 isa member of the 68HC05K series of devices whichare available in 16-pin DIL or SOIC packages.It uses the same CPU as the other devices in the68HC05 family and has the same instructions andregisters. Additionally, the device has a 15-stagemulti-function timer and 10 general purposebi-directional I/0 lines. A mask option is availablefor software programmable pull-downs on all ofthe I/O pins and four of the pins are capable ofgenerating interrupts.The device is ideally suited for remote-controlkeyboard applications because the pull-downs andthe interrupt drivers on the port pins allowkeyboards to be built without any externalcomponents except the keys themselves. There isno need for external pull-up or pull-down resistors,or diodes for wired-OR interrupts, as these featuresare already designed into the device.
標(biāo)簽： Infra-red Remote Cont 05K
上傳時(shí)間： 2014-01-24
上傳用戶：zl5712176
基于單片機(jī)的汽車多功能報(bào)警系統(tǒng)設(shè)計(jì)The Design of Automobile Multi-function AlarmingBased on Single Chip Computer劉法治趙明富寧睡達(dá)(河 南 科 技 學(xué) 院 ，新 鄉(xiāng) 453 00 3)摘要介紹了一種基于單片機(jī)控制的汽車多功能報(bào)警系統(tǒng)，它能對(duì)汽車的潤(rùn)滑系統(tǒng)油壓、制動(dòng)系統(tǒng)氣壓、冷卻系統(tǒng)溫度、輪胎欠壓及防盜進(jìn)行自動(dòng)檢測(cè)，并在發(fā)現(xiàn)異常情況時(shí)，發(fā)出聲光報(bào)警。闡述了該報(bào)警系統(tǒng)的硬件組成及軟件設(shè)計(jì)方法。關(guān)鍵詞單片機(jī)傳感器數(shù)模轉(zhuǎn)換報(bào)警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly場(chǎng)thesystem. Audio and visual alarms wil be provided under abnormal conditions廠The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽車多功能報(bào)苦器硬件系統(tǒng)設(shè)計(jì)根據(jù) 系 統(tǒng) 實(shí)際需要和產(chǎn)品性價(jià)比，選用ATMEL公司新生產(chǎn)的采用CMOs工藝的低功耗、高性能8位單片機(jī)AT89S52作為系統(tǒng)的控制器。AT89S52的片內(nèi)有8k Bytes LSP Flash閃爍存儲(chǔ)器，可進(jìn)行100(〕次寫、擦除操作;256Bytes內(nèi)部數(shù)據(jù)存儲(chǔ)器(RAM);3 2 根可編程輸N輸出線;2個(gè)可編程全雙工串行通道;看門狗(WTD)電路等。系統(tǒng)由傳感器、單片機(jī)、模數(shù)轉(zhuǎn)換器、無(wú)線信號(hào)發(fā)射電路、指示燈驅(qū)動(dòng)電路、聲光報(bào)警驅(qū)動(dòng)電KD一9563，發(fā)出三聲二閃光。并觸發(fā)一個(gè)高電平，驅(qū)動(dòng)無(wú)線信號(hào)發(fā)射電路。
標(biāo)簽： 單片機(jī) 汽車 多功能 報(bào)警
上傳時(shí)間： 2013-11-09
上傳用戶：gxmm
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
同步技術(shù)是跳頻通信系統(tǒng)的關(guān)鍵技術(shù)之一，尤其是在快速跳頻通信系統(tǒng)中，常規(guī)跳頻通信通過(guò)同步字頭攜帶相關(guān)碼的方法來(lái)實(shí)現(xiàn)同步，但對(duì)于快跳頻來(lái)說(shuō)，由于是一跳或者多跳傳輸一個(gè)調(diào)制符號(hào)，難以攜帶相關(guān)碼。對(duì)此引入雙跳頻圖案方法，提出了一種適用于快速跳頻通信系統(tǒng)的同步方案。采用短碼攜帶同步信息，克服了快速跳頻難以攜帶相關(guān)碼的困難。分析了同步性能，仿真結(jié)果表明該方案同步時(shí)間短、虛警概率低、捕獲概率高，同步性能可靠。 Abstract: Synchronization is one of the key techniques to frequency-hopping communication system， especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems， synchronization can be achieved by synchronization-head which can be used to carry the synchronization information， but for the fast frequency hopping， Because modulation symbol is transmitted by per hop or multi-hop， it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code， a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code， which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed， and simulation results show that the scheme has the advantages of shorter synchronization time， lower probability of false alarm， higher probability of capture and more reliable of synchronization.
標(biāo)簽： 快速跳頻 同步技術(shù) 通信系統(tǒng)
上傳時(shí)間： 2013-11-23
上傳用戶：mpquest
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時(shí)間： 2014-01-17
上傳用戶：Altman
Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
標(biāo)簽： 時(shí)鐘恢復(fù) 英文
上傳時(shí)間： 2013-10-30
上傳用戶：ysjing
ARM通訊 H-JTAG 是一款簡(jiǎn)單易用的的調(diào)試代理軟件，功能和流行的MULTI-ICE 類似。H-JTAG 包括兩個(gè)工具軟件：H-JTAG SERVER 和H-FLASHER。其中，H-JTAG SERVER 實(shí)現(xiàn)調(diào)試代理的功能，而H-FLASHER則實(shí)現(xiàn)了FLASH 燒寫的功能。H-JTAG 的基本結(jié)構(gòu)如下圖1-1所示。 H-JTAG支持所有基于ARM7 和ARM9的芯片的調(diào)試，并且支持大多數(shù)主流的ARM調(diào)試軟件，如ADS、RVDS、IAR 和KEIL。通過(guò)靈活的接口配置，H-JTAG 可以支持WIGGLER，SDT-JTAG 和用戶自定義的各種JTAG 調(diào)試小板。同時(shí)，附帶的H-FLASHER 燒寫軟件還支持常用片內(nèi)片外FLASH 的燒寫。使用H-JTAG，用戶能夠方便的搭建一個(gè)簡(jiǎn)單易用的ARM 調(diào)試開發(fā)平臺(tái)。H-JTAG 的功能和特定總結(jié)如下： 1. 支持 RDI 1.5.0 以及 1.5.1； 2. 支持所有ARM7 以及 ARM9 芯片； 3. 支持 THUMB 以及ARM 指令； 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN； 5. 支持 SEMIHOSTING； 6. 支持 WIGGLER， SDT-JTAG和用戶自定義JTAG調(diào)試板； 7. 支持 WINDOWS 9.X/NT/2000/XP； 8．支持常用FLASH 芯片的編程燒寫； 9. 支持LPC2000 和AT91SAM 片內(nèi)FLASH 的自動(dòng)下載；
標(biāo)簽： H-JTAG 調(diào)試軟件
上傳時(shí)間： 2014-12-01
上傳用戶：Miyuki
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時(shí)間： 2013-11-10
上傳用戶：yy_cn
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽： RocketIO Virtex XAPP 713
上傳時(shí)間： 2013-12-25
上傳用戶：jkhjkh1982
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