PCI總線是目前最為流行的一種局部性總線 通過對PCI總線一些典型功能的分析以及時序的闡述，利用VetilogHDL設(shè)計了一個將非PCI功能設(shè)備轉(zhuǎn)接到PC1總線上的IP Core 同時，通過在ModeISim SE PLUS 6．0 上運行測試程序模塊，得到了理想的仿真數(shù)據(jù)波形，從軟件上證明了功能的實現(xiàn)。
標(biāo)簽： VeriIog Core PCI HDL
上傳時間： 2014-12-30
上傳用戶：himbly
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
上傳時間： 2013-11-01
上傳用戶：KSLYZ
作為一種獨立于處理器的局部總線,PCI非常適用于網(wǎng)絡(luò)適配器、硬盤驅(qū)動器、全動態(tài)視頻卡、圖形卡及各類高速外設(shè)。據(jù)稱,目前有90%的Pentium處理器采用PCI做為系統(tǒng)總線。
上傳時間： 2013-11-07
上傳用戶：liaocs77
PCI Express是由Intel，Dell，Compaq，IBM，Microsoft等PCI SIG聯(lián)合成立的Arapahoe Work Group共同草擬并推舉成取代PCI總線標(biāo)準(zhǔn)的下一代標(biāo)準(zhǔn)。PCI Express利用串行的連接特點能輕松將數(shù)據(jù)傳輸速度提到一個很高的頻率，達(dá)到遠(yuǎn)遠(yuǎn)超出PCI總線的傳輸速率。一個PCI Express連接可以被配置成x1，x2，x4，x8，x12，x16和x32的數(shù)據(jù)帶寬。x1的通道能實現(xiàn)單向312.5 MB／s（2.5 Gb／s）的傳輸速率。Xilinx公司的Virtex5系列FPGA芯片內(nèi)嵌PCI-ExpressEndpoint Block硬核，為實現(xiàn)單片可配置PCI-Express總線解決方案提供了可能。 本文在研究PCI-Express接口協(xié)議和PCI-Express Endpoint Block硬核的基礎(chǔ)上，使用Virtex5LXT50 FPGA芯片設(shè)計PCI Express接口硬件電路，實現(xiàn)PCI-Express數(shù)據(jù)傳輸
上傳時間： 2013-12-27
上傳用戶：wtrl
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
PCI-PCI 橋啟動時，一般需要從EEPROM 預(yù)讀取配置數(shù)據(jù)。更改EEPROM中的數(shù)據(jù)一般需要專用的燒結(jié)器，這給調(diào)試過程帶來不便。尤其是采用表貼封裝的EEPROM。本文以Intel 公司的Dec21554PCI-PCI 橋為例，介紹一種在線讀寫EEPROM 的方法。EEPROM選用的是ATMEL 公司生產(chǎn)的AT93LC66，4Kbit，按512×8bit 組織。
上傳時間： 2013-11-08
上傳用戶：trepb001
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-20
上傳用戶：dave520l
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2014-01-24
上傳用戶：s363994250
PCI-E是一種高速傳輸總線形式。
標(biāo)簽： PCI-E 8622 數(shù)據(jù)采集卡
上傳時間： 2013-12-18
上傳用戶：宋桃子
PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊
上傳時間： 2013-10-22
上傳用戶：ssz1990
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