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Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
標簽：
representation
Magnitude
the
magnitude
上傳時間：
2013-12-24
上傳用戶：金宜
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design LP,HP,B S digital Butterworth and Chebyshev
filter. All array has been specified internally,so user only need to
input f1,f2,f3,f4,fs(in hz), alpha1,alpha2(in db) and iband (to specify
the type of to design). This program output hk(z)=bk(z)/ak(z),k=1,2,...,
ksection and the freq.
標簽：
Butterworth
internally
Chebyshev
specified
上傳時間：
2015-11-08
上傳用戶：253189838
-
About:
hamsterdb is a database engine written in ANSI C. It supports a B+Tree index structure, uses memory mapped I/O (if available), supports cursors, and can create in-memory databases.
Release focus: Major feature enhancements
Changes:
This release comes with many changes and new features. It can manage multiple databases in one file. A new flag (HAM_LOCK_EXCLUSIVE) places an exclusive lock on the file. hamsterdb was ported to Windows CE, and the Solution file for Visual Studio 2005 now supports builds for x64. Several minor bugs were fixed, performance was improved, and small API changes occurred. Pre-built libraries for Windows (32-bit and 64-bit) are available for download.
Author:
cruppstahl
標簽：
C.
hamsterdb
structure
database
上傳時間：
2013-12-11
上傳用戶：LouieWu
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Floyd-Warshall算法描述
1)適用范圍：
a)APSP(All Pairs Shortest Paths)
b)稠密圖效果最佳
c)邊權可正可負
2)算法描述：
a)初始化：dis[u,v]=w[u,v]
b)For k:=1 to n
For i:=1 to n
For j:=1 to n
If dis[i,j]>dis[i,k]+dis[k,j] Then
Dis[I,j]:=dis[I,k]+dis[k,j]
c)算法結束：dis即為所有點對的最短路徑矩陣
3)算法小結：此算法簡單有效，由于三重循環結構緊湊，對于稠密圖，效率要高于執行|V|次Dijkstra算法。時間復雜度O(n^3)。
考慮下列變形：如(I,j)∈E則dis[I,j]初始為1,else初始為0，這樣的Floyd算法最后的最短路徑矩陣即成為一個判斷I,j是否有通路的矩陣。更簡單的，我們可以把dis設成boolean類型，則每次可以用“dis[I,j]:=dis[I,j]or(dis[I,k]and dis[k,j])”來代替算法描述中的藍色部分，可以更直觀地得到I,j的連通情況。
標簽：
Floyd-Warshall
Shortest
Pairs
Paths
上傳時間：
2013-12-01
上傳用戶：dyctj
-
PCI設計指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.
標簽：
interface
PCI
pre-implemented
LogiCORE
上傳時間：
2016-04-03
上傳用戶：清風冷雨
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The Cyclone® III PCI development board provides a hardware platform for developing and
prototyping low-power, high-performance, logic-intensive PCI-based designs. The board provides a
high-density of the memory to facilitate the design and development of FPGA designs which need
huge memory storage, and also includes Low-Voltage Differential Signaling (LVDS) interface of
the High-Speed Terasic Connectors (HSTCs) for extra high-speed interface application.
標簽：
development
developing
prototypi
provides
上傳時間：
2017-01-29
上傳用戶：jjj0202
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basic.c */
/**//* Project:NeuroBasic, basic package*//**/
/* Survey:This is a simple Basic b-code compiler which*/
/*can be used as a comfortable command shell for */
/* any program. The actual compiler is found in */
/*compiler.c.*/
/*The functions m_fctptr() and user_server()*/
/*build an interface to an
標簽：
basic
NeuroBasic
Project
package
上傳時間：
2017-02-15
上傳用戶：xymbian
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該程序用以查找任意兩個整數之間的所有素數。 Prime number finder can find all primes between a and b and will write the results to the file PRIMES.TXT
標簽：
and
between
number
finder
上傳時間：
2014-01-14
上傳用戶：cccole0605
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FEATURES
• 16 bit PIPE Spec PCI Express Testbench
• Link training
• Initial Flow Control
• Packet Classes for easy to build PHY,DLLP and TLP packets
• DLLP 16 bit CRC and TLP LCRC generation
• Sequence Number generation and checking
• ACK TLP packets
• Scrambling
• MemRd MemWr CfgRd CfgWr TLPs
標簽：
8226
Testbench
FEATURES
training
上傳時間：
2014-01-18
上傳用戶：netwolf
-
The PCI Special Interest Group disclaims all warranties and liability for the use of this document
and the information contained herein and assumes no responsibility for any errors that may appear
in this document, nor does the PCI Special Interest Group make a commitment to update the
information contained herein.
標簽：
warranties
disclaims
liability
Interest
上傳時間：
2013-12-26
上傳用戶：leixinzhuo
