Analysis of blind data hiding using discrete cosine transform phase modulation。
標簽： modulation transform Analysis discrete
上傳時間： 2013-12-27
上傳用戶：yzy6007
編譯原理大作業---tiger編譯器 包括semant,translate,mipsframe,regalloc等所有phase 懂的人自會知道
標簽： mipsframe translate regalloc semant
上傳時間： 2016-11-01
上傳用戶：lanwei
GPS Data processing: Code and Phase
標簽： processing Phase Data Code
上傳時間： 2013-12-12
上傳用戶：sunjet
This m file simulates a differential phase shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
標簽： differential bandwidth simulates system
上傳時間： 2014-01-03
上傳用戶：784533221
script for generting transmit waveforms in a minimum shift keying, a form of continuous phase frequency shift keying
標簽： continuous generting waveforms transmit
上傳時間： 2016-11-30
上傳用戶：ANRAN
A high-speed variable phase accumulator for an ADPLL architecture
標簽： architecture accumulator high-speed variable
上傳時間： 2013-11-26
上傳用戶：wpt
A Top-Down Verilog-A Design on the digital phase-Lockedmloop
標簽： phase-Lockedmloop Verilog-A Top-Down digital
上傳時間： 2013-12-02
上傳用戶：silenthink
Ethernet Services Attributes Phase
標簽： Attributes Ethernet Services Phase
上傳時間： 2013-12-13
上傳用戶：xhz1993
A Matlab code to plot the matched filter for 16-element linear array with constant phase weights on transmit and receive LFM waveform parameters.計算具有收發線性調頻波形參數的相位權重的16單元線性匹配濾波器
標簽： constant matched element weights
上傳時間： 2014-07-19
上傳用戶：siguazgb
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
